... reprogrammed to fix errors later. A synthesis tool is used to read in the VHDL description and map the description to the target programmable logic device. The synthesis tool reads all the VHDL ... 15 CPU Design: Synthesis Results After the CPU has been functionally verified, the design can be implemented in actual hardware. This chapter describes the synthesis process and synthesis results ... (elaborate), optimizes the design, and then maps the optimized description to the target tech- nology. The synthesis tool used is the Leonardo Spectrum synthesis tool from Exemplar Logic. This is a popular...