CHAPTER 15 CPU Design: Synthesis Results After the CPU has been functionally verified, the design can be implemented in actual hardware. This chapter describes the synthesis process and synthesis results of the CPU RTL description. The VHDL design description is optimized and mapped to a programmable logic device. As opposed to an ASIC device, these devices can be pro- grammed by designers at their desks, and most can be reprogrammed to fix errors later. A synthesis tool is used to read in the VHDL description and map the description to the target programmable logic device. The synthesis tool reads all the VHDL source files, links them together (elaborate), optimizes the design, and then maps the optimized description to the target tech- nology. The synthesis tool used is the Leonardo Spectrum synthesis tool from Exemplar Logic. This is a popular syn- thesis tool in the FPGA (Field Programmable Gate Array) market and produces very good results quickly. 15 Chapter Fifteen 358 The first step in the synthesis process is to read all the files of the design into the synthesis tool. This can be accomplished either by using the synthesis tool GUI (Graphical User Interface) or by issuing command language commands. First time or casual users will probably use the GUI because no command language syntax knowledge is required, and all operations can be accomplished through menu clicks. Everyday users of the tool quickly learn the command language of the synthesis tool, create scripts that build up the design, and run those scripts to create the design. This provides a repeatable method of creating the design. The Leonardo Spectrum GUI is shown in Figure 15-1. Leonardo Spectrum contains a Quick Setup guide that allows the designer to easily specify the source files for the design, the target tech- nology, the target device and speed grade, the clock frequency, and the out- put file. Once this information has been specified, the flow can be run to cre- ate the netlist for the target device. This example will use the Advanced GUI because the hierarchy will be preserved to get a better idea of the size of each design block. The first step is to select the Technology tab. In this section the tar- get technology will be set: the device package and the speed grade of the target technology. In this example we chose Altera Apex 20KE technology Figure 15-1 Leonardo Spectrum User Interface. 359 CPU Design: Synthesis Results as the target technology. Then a default package is chosen, and the actual package can be selected from a list. We use the EP20K200EFC484 package because this design will be targeted to that device. The speed grade deter- mines how fast the device will operate. In this example we use the fastest device, the 2X speed grade. These settings are shown in Figure 15-2. Fi- nally the target technology is loaded into the synthesis tool by selecting the Load Library button. Our next step is to read the VHDL files into the synthesis tool by selecting the Input tab. The result is shown in Figure 15-3. We then select the File Folder button next to the Working Directory text. This brings up the working directory selection box (see Figure 15-4). We choose the working directory by navigating to the directory containing the design source files. The source files can now be read into Leonardo Spectrum using the S ET Input Files dialog box. We select the file folder button next to the Open Files text (see Figure 15-3). This dialog box allows us to select one or more files to be added to the list of files for the design. In Figure 15-5 all the design files are selected except the testbench ( mem2.vhd ) and top level that instantiates the testbench ( top.vhd ). Clicking the Open button will add all the files to the design file list. Figure 15-2 Leonardo Spectrum Technology Tab. Chapter Fifteen 360 Figure 15-3 Select Input Files Dia- log Box. Figure 15-4 Set Working Directory. The order that the files are read in is determined by the order in the list. The first to be read is the top of the list. In VHDL the order of reading files is important so that package files are read in before they are used. Also the top level of the design should be read in last so that the design is properly elaborated. In Figure 15-6 the list of files has been reordered so that the package file, cpulib.vhd , is now read first, and the design top level, cpu.vhd , is now read last. Files are moved in the list by selecting them, and dragging and dropping to the new location. Now that the files are in the proper order all the design files can be read into the synthesis tool by selecting the Read button. Now that the design has been read into the system, constraints can be placed on the design to control how the design is implemented. For in- stance timing constraints, input constraints, and output constraints can all be entered at this point. For this example we will only enter a clock constraint. The clock constraint will specify the minimum clock frequency for the design. This will give the synthesis tool a target frequency with which to implement all logic. The clock constraint is specified as shown in Figure 15-7. Now that the library has been loaded, the design files read in, and the constraints specified, the design can be optimized. Select the Optimize tab to invoke the optimization user interface. For this example optimizing for area is used to create a small design. The hierarchy of the design will be preserved to get an idea of the size of each block. In general if the design 361 CPU Design: Synthesis Results Figure 15-5 Select Input Files. is small enough, removing the hierarchy will create a smaller and faster design. Finally IO pads will not be added to the design as the Altera place and route tool will do this automatically. The optimize user interface with all the switches set is shown in Figure 15-8. Selection of the Optimize button will perform the optimization process and implement the specified design with Apex 20KE technology primitives. The Report tab is used to generate area and timing reports. An area report gives the size of the design based on the design implementation in the target technology. To generate a report, select the Report Area Chapter Fifteen 362 Figure 15-6 Set Order of Input Files. button as shown in Figure 15-9. The report generated will look like the one shown below: ->report_area -cell_usage -all_leafs ******************************************************* Cell: cpu View: rtl Library: work cpu ******************************************************* Cell Library References Total Area GND apex20e 1 x 1 1 GND 363 CPU Design: Synthesis Results Figure 15-7 Set Clock Constraint to 30 Mhz. TRI apex20e 16 x 1 16 TRIs VCC apex20e 1 x 1 1 VCC alu work 1 x 1 1 GND 156 156 LCs apex20_lcell_normal apex20e 33 x 1 33 LCs comp work 1 x 26 26 LCs control work 1 x 108 108 LCs 1 1 GND 1 1 VCC 384 384 Memory Bits Chapter Fifteen 364 Figure 15-8 Optimize Design. reg work 1 x 11 11 LCs 1 1 GND reg work 1 x 16 16 LCs 1 1 GND regarray_notri work 1 x 1 1 VCC 128 128 Memory Bits shift work 1 x 1 1 shift trireg_notri work 3 x 16 48 LCs 1 3 GND Number of ports : 37 365 CPU Design: Synthesis Results Figure 15-9 Report Area. Number of nets : 198 Number of instances : 61 Number of references to this view: 0 total accumulated area: DELAY flex10 8 x Number of GND : 8 Number of LCs : 398 Number of Memory Bits : 512 Number of TRIs : 16 Number of VCC : 1 Number of SHIFT : 1 Number of accumulated instances : 443 *********************************************** Device Utilization for EP20K200EFC484 *********************************************** Resource Used Avail Utilization ----------------------------------------------- IOs 37 376 9.84% LCs 398 8320 4.78% Memory Bits 512 106496 0.48% ----------------------------------------------- Info, Command 'report_area' finished successfully The last step in the synthesis process is to write out a gate-level description for the optimized design. For this example the output format used will be EDIF. The common term for this output file is a netlist, because it describes the primitives used in the design and the signals (or nets—short for networks) used to connect these primitives. To generate the netlist select the Output tab, modify the name of the output file as neces- sary, and then select the Write button. This is shown in Figure 15-10. This netlist will now be passed to the Altera place and route tools to create the actual implementation of the device. This process is described in the next chapter. SUMMARY In this chapter, we synthesized all of the VHDL RTL descriptions of the CPU and analyzed the results. In the next chapter, we read the synthesized netlist into the place and route tools, and run the place and route to imple- ment the design in the target technology. Chapter Fifteen 366 [...].. .CPU Design: Synthesis Results Figure 15-10 367 This page intentionally left blank . CHAPTER 15 CPU Design: Synthesis Results After the CPU has been functionally verified, the design can be implemented. implemented in actual hardware. This chapter describes the synthesis process and synthesis results of the CPU RTL description. The VHDL design description is