... at VHDL:Example 2•Declare a 3- input AND gateABCY 3- input AND gateentity AND3 isport ( A,B,C: in bit;Y: out bit);end entity AND3;architecture RTL of AND3 isbeginY <= ‘1’ when ((A=‘1’) ... at VHDL:Example 2•Declare a 3- input OR gateABCY 3- input OR gateentity OR3 isport ( A,B,C: in bit;Y: out bit);end entity OR3;architecture RTL of OR3 isbeginY <= ‘0’ when ((A=‘0’) ... 3 •Assume that we want to use the previously declared AND3, OR3 and INV for this structural description of MUXconfiguration Use3InputGates of MUX21 isfor Behavend for;for Structfor Gate1:INV...