Đang tải... (xem toàn văn)
Bộ môn Điện tử số do Thầy Nam phó viên trưởng trường ĐHBKHN biên soạn đem lại cho các bạn 1 cách tiếp cận đơn giản dễ hiểu với môn này
3/1 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Course contents • Digital design • Combinatorial circuits: without status Sequential circuits: with status • FSMD design: hardwired processors • Language based HW design: VHDL 3/2 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Sequential Circuits • The flip-flop as building block • Design of synchronous sequential circuits • Design of asynchronous sequential circuits • Basic RTL building blocks 3/3 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Sequential Circuits The flip-flop as building block • Design of synchronous sequential circuits • Design of asynchronous sequential circuits • Basic RTL building blocks 3/4 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL The flip-flop as building block • Definitions: Combinatorial circuit: the output is function of the current value of the inputs Sequential circuit: the output is function of the current value of the inputs and of the current state (i.e. also function of the sequence of past inputs) 3/5 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL The flip-flop as building block • Definitions Asynchronous sequential circuits: outputs and state change as soon as an input changes Synchronous sequential circuits: outputs and state change only when a special input, the clock, gets a certain value Clock period: duration between two consecutive 1→0 transitions of the clock Clock frequency: 1 / (clock period) Duty cycle: (duration that the clock equals 1) / (clock period) Rising edge: 0→1 transition of the clock Falling edge: 1→0 transition of the clock 3/6 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Sequential Circuits • The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop types • Design of synchronous sequential circuits • Design of asynchronous sequential circuits • Basic RTL building blocks 3/7 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Sequential Circuits • The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop types • Design of synchronous sequential circuits • Design of asynchronous sequential circuits • Basic RTL building blocks 3/8 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL SR Latch Set Reset Q’ Q S R Q Q’ Undefined S R Q(next) 0 0 Q 0 1 0 1 0 1 1 1 NA 3/9 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL SR Latch • Note that a Boolean signal now already consists of 5 values: 0: the logical signal “0” 1: the logical signal “1” x: don’t care Z: high impedant U: undefined • The oscillation is called critical race • The oscillation only happens when the delay of both gates is exactly equal • When the delays are not equal, the fastest gates determines the end result: implementation and run-time dependent ⇒ undefined 3/10 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL SR Latch Set Reset Q Q’ S R Q(next) 1 1 Q 1 0 0 0 1 1 0 0 NA Set and Reset active low S R Q Q’ [...]... R.Lauwereins Imec 2001 Level sensitive latch X Digital design Combinatorial circuits D Q1 4 /3 C Clk Sequential circuits FSMD design VHDL Clk X Q1 Q2 Q3 Two solutions: • Master-slave • Edge-triggered 3/ 21 D Q2 4 /3 C D Q3 4 /3 C Y © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 22 Sequential Circuits • The flip-flop as building block SR Latch Gated SR Latch... Combinatorial circuits Sequential circuits FSMD design VHDL Clk Master D Qm1 4 /3 C Slave D Qs1 4 /3 C Q1 Master D Qm2 4 /3 C Slave D Qs2 4 /3 C Clk X Qm1 Q1 Qm2 Y 3/ 23 The master clocks at the falling clock edge The slave clocks at the rising edge Y © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 24 Sequential Circuits • The flip-flop as building block SR Latch... circuits Q(next) 0 1 Clk Q’ 0 1 FSMD design VHDL Excitation table (for design with D flip-flop) Q Designing with D flip-flop is easy 3/ 32 Q(next) D 0 0 1 1 0 1 0 1 0 1 0 1 © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 33 Sequential Circuits • The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop... (for design with JK flip-flop) Circuits that use JK flip-flops are cheaper than those using SR flip-flops: more don’t cares 3/ 30 Q Q(next) J K 0 0 1 1 0 1 0 1 0 1 x x x x 1 0 © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 31 Sequential Circuits • The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity... design VHDL D C S D’ R 3/ 16 S © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Gated D Latch D S Q’ Clock R Q Sequential circuits FSMD design C=1: follow input C=0: latch output C D Q(next) 0 0 1 1 0 1 0 1 Q Q 0 1 Analogously, D may not switch “immediately after” H-to-L of the clock (during the hold time) VHDL Symbol D Q 5.2 /3. 8 C Q’ 3/ 17 Given values: 5.2=C to QL→H 3. 8=C to QH→L © R.Lauwereins... flip-flop) Q T Sequential circuits Q(next) 0 1 Clk Q’ Q Q’ FSMD design VHDL Excitation table (for design with T flip-flop) T D Q Clk Q’ 3/ 34 Q Q(next) T 0 0 1 1 0 1 0 1 0 1 1 0 © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 35 Sequential Circuits • The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop... Digital design Combinatorial circuits Set Clk Sequential circuits FSMD design VHDL D Clk D B A R S 3/ 25 Set Latch Q Q Reset B Output Latch Q’ Reset Latch © R.Lauwereins Imec 2001 Sequential Circuits • The flip-flop as building block Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 26 SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop types SR flip-flop... level triggered R Q(next) 0 0 1 1 Clk R Q’ Positive level triggered 3/ 28 Characteristic table (for design of SR flip-flop) 0 1 0 1 Q 0 1 NA Excitation table (for design with SR flip-flop) Q Q(next) S R 0 0 1 1 0 1 0 1 0 1 0 x x 0 1 0 © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 29 Sequential Circuits • The flip-flop as building block SR Latch... circuits FSMD design VHDL 3/ 11 Sequential Circuits • The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop types • Design of synchronous sequential circuits • Design of asynchronous sequential circuits • Basic RTL building blocks © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 12 Gated SR Latch... outputs Q’ Clock Q Reset C S R Q(next) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q Q Q Q Q 0 1 NA © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 3/ 13 Sequential Circuits • The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop types • Design of synchronous sequential circuits • Design of asynchronous . “immediately after” H-to-L of the clock (during the hold time) S R 5.2 /3. 8 D C Q Q’ Symbol Given values: 5.2=C to Q L→H 3. 8=C to Q H→L 3/ 18 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Sequential. blocks 3/ 8 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL SR Latch Set Reset Q’ Q S R Q Q’ Undefined S R Q(next) 0 0 Q 0 1 0 1 0 1 1 1 NA 3/ 9 ©. Q 1 0 0 Q 1 0 1 0 1 1 0 1 1 1 1 NA C=1: follow inputs C=0: latch outputs Set Reset Q’ Q Clock 3/ 13 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Sequential