... on an FPGA has a single-clock latency Based on the complexity assessment in this section and the fact that we target an FPGA implementation where a number of dedicated multipliers are available, ... enhances numerical stability; and (d) an aggressive time-shared VLSI architecture The above techniques are quite general and are readily applicable to any MMSE- based MIMO detector implementation CONCLUSION ... [3] A J Paulraj and C B Papadias, “Space-time processing for wireless communications,” IEEE Signal Processing Magazine, vol 14, no 6, pp 49–83, 1997 [4] A J Paulraj, D A Gore, R U Nabar, and...