Data Sheet High-Performance, Enhanced Flash Microcontrollers phần 1 docx

... 11 11 111 1 11 11 111 1 uuuu uuuuOSCCON 242 442 252 452 0 0 uLVDCON 242 442 252 452 00 010 1 00 010 1 uu uuuuWDTCON 242 442 252 452 0 0 uRCON(4)242 442 252 452 0 q 11 qq 0 q qquu u u qquuTMR1H ... 252 452 0000 000x 0000 000u uuuu uuuu (1) INTCON2 242 442 252 452 11 11 -1- 1 11 11 -1- 1 uuuu -u-u (1) INTCON3 242 442 252 452 11 -0 0-00 11 -0 0-00 uu-u u-uu (1) INDF0 242 442 252 452 N/A N/A N/APOSTINC0 ... uuuuTMR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuuT1CON 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuuTMR2 242 442 252 452 0000 0000 0000 0000 uuuu uuuuPR2 242 442 252 452 11 11 111 1 11 11 111 1...

... TMR2IP TMR1IP 0000 0000 0000 0000TRISC PORTC Data Direction Register 11 11 111 1 11 11 111 1TMR2 Timer2 Module Register 0000 0000 0000 0000PR2 Timer2 Module Period Register 11 11 111 1 11 11 111 1T2CON— ... 11 1 = 1: 256 prescale value 11 0 = 1: 128 prescale value 10 1 = 1: 64 prescale value 10 0 = 1: 32 prescale value 011 = 1: 16 prescale value 010 = 1: 8 prescale value0 01 = 1: 4 prescale value000 = 1: 2 ... xxxx uuuu uuuuLATD LATD Data Output bits xxxx xxxx uuuu uuuuTRISD PORTD Data Direction bits 11 11 111 1 11 11 111 1PORTE— — — — —RE2RE1RE0 -000 -000LATE— — — — — LATE Data Output bits -xxx -uuuTRISE...

... 10 RA1/AN1 10 RA2/AN2/VREF- 10 RA3/AN3/VREF+ 10 RA4/T0CKI 10 RA5/AN4/SS/LVDIN 10 RB0/INT0 11 RB1/INT1 11 RB2/INT2 11 RB3/CCP2 11 RB4 11 RB5/PGM 11 RB6/PGC 11 RB7/PGD 11 RC0/T1OSO/T1CKI 12 RC1/T1OSI/CCP2 ... Interrupt 11 1, 11 2, 12 2Timer3 11 3Associated Registers 11 5Operation 11 4Oscillator 11 3, 11 5Overflow Interrupt 11 3, 11 5Special Event Trigger (CCP) 11 5TMR3H Register 11 3TMR3L Register 11 3Timing ... 13 RA2/AN2/VREF- 13 RA3/AN3/VREF+ 13 RA4/T0CKI 13 RA5/AN4/SS/LVDIN 13 RB0/INT 14 RB1 14 RB2 14 RB3 14 RB4 14 RB5/PGM 14 RB6/PGC 14 RB7/PGD 14 RC0/T1OSO/T1CKI 15 RC1/T1OSI/CCP2 15 RC2/CCP1 15 RC3/SCK/SCL 15 RC4/SDI/SDA...

... 452 0000 -11 1 0000 -11 1 uuuu -uuu TRISD242 442 252 452 11 11 111 1 11 11 111 1 uuuu uuuu TRISC 242 442 252 452 11 11 111 1 11 11 111 1 uuuu uuuu TRISB 242 442 252 452 11 11 111 1 11 11 111 1 uuuu uuuu ... DS39564C-page 31 PIC18FXX2IPR2 242 442 252 452 1 111 1 1 111 1 u uuuu PIR2 242 442 252 452 0 0000 0 0000 u uuuu (1) PIE2 242 442 252 452 0 0000 0 0000 u uuuu IPR1242 442 252 452 11 11 111 1 11 11 111 1 uuuu ... REG20 010 010 0 0000 0000 ADDWF REG3 ; continue codeCASE 2:Object Code Source Code 011 0 011 0 0000 0000 TSTFSZ REG1 ; is RAM location 0? 11 00 00 01 0 010 0 011 MOVFF REG1, REG2 ; Yes 11 11 010 0 010 1 011 0...

... Register 11 11 111 1 11 11 111 1INTCONGIE/GIEHPEIE/GIELTMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000uINTCON2 RBPU INTEDG0 INTEDG1 INTEDG2— TMR0IP —RBIP 111 1 -1- 1 11 11 -1- 1INTCON3 ... xxxx uuuu uuuuTRISD PORTD Data Direction Register 11 11 111 1 11 11 111 1TRISEIBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -11 1 0000 -11 1Legend: x = unknown, u = unchanged, - = unimplemented, ... xxxx xxxx uuuu uuuuLATC LATC Data Output Register xxxx xxxx uuuu uuuuTRISC PORTC Data Direction Register 11 11 111 1 11 11 111 1Legend: x = unknown, u = unchangedPIC18FXX2DS39564C-page 70 © 2006...

... DS39564C-page 14 3PIC18FXX2FIGURE 15 -11 : I2C SLAVE MODE TIMING (TRANSMISSION, 10 -BIT ADDRESS) SDASCLSSPIF BF (SSPSTAT<0>)S 1 234 56 7 89 1 2345 67 89 12 345 789P 1 111 0A9A8 A7 A6A5A4A3A2A1A0 ... DS39564C-page 14 7PIC18FXX2FIGURE 15 -14 : I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10 -BIT ADDRESS) SDASCLSSPIF BF (SSPSTAT<0>)S 1 234 56 7 8 9 1 2345 67 89 1 2345 789P 1 1 1 1 0 A9A8 ... requirement for SCL (seeFigure 15 -12 ).FIGURE 15 -12 : CLOCK SYNCHRONIZATION TIMINGSDASCLDX-1DXWRQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4SSPCONCKPMaster...

... 11 10 = 4.5V - 4.77V 11 01 = 4.2V - 4.45V 11 00 = 4.0V - 4.24V 10 11 = 3.8V - 4.03V 10 10 = 3.6V - 3.82V 10 01 = 3.5V - 3.71V 10 00 = 3.3V - 3.50V 011 1 = 3.0V - 3 .18 V 011 0 = 2.8V - 2.97V 010 1 ... +1. 73 19 19 .53 +1. 73 15 76.8 78 .13 +1. 73 7 73.66 -4.09 6 78 .13 +1. 73 4 78 .13 +1. 73 396 89.29 -6.99 6 10 3 .13 +7.42 4 97.66 +1. 73 3 10 4 .17 +8. 51 2300 312 .50 +4 .17 1 257. 81 -14 .06 1 NA - - 312 .50 ... Direction Register 11 11 11 11 111 1PORTE — — — — —RE2RE1RE0 -000 -000LATE — — — — — LATE2 LATE1 LATE0 -xxx -uuuTRISEIBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -11 1 0000 -11 1Legend: x...

... Standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2)2 1 (2) 1 (2) 1 (2)2 1 12 1 1 1 12 1 222 1 111 0 11 10 11 10 11 10 11 10 11 10 11 10 11 01 111 0 11 10 11 11 00000000 11 10 11 11 0000 11 11 00000000 11 01 000000000000000000000 010 011 00 011 011 1 010 100 01 010 00nnn0000 11 0skkkk00000000 11 11 kkkk0000xxxx000000001nnn00000000 11 0000000000nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnkkkkkkkk00000000kkkkkkkk0000xxxx00000000nnnn 11 11 00 01 kkkk00 01 0000nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnkkkkkkkk 010 0 011 1kkkkkkkk0000xxxx 011 0 010 1nnnn 11 11 000skkkk001s0 011 NoneNoneNoneNoneNoneNoneNoneNoneNoneNoneTO, ... 3) 1 0 010 0 010 00 01 011 000 01 011 0 011 0 011 000000 010 010 00 010 0 011 010 000 01 010 1 11 00 11 11 011 00000 011 00 011 010 00 011 010 0 011 0 010 1 010 1 010 10 011 011 000 01 01da00da01da 10 1a 11 da001a 010 a000a01da 11 da 11 da 10 da 11 da 10 da00da00daffffffff 11 1a001a 11 0a01da01da00da00da 10 0a01da 11 da 10 da 10 da 011 a 10 daffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffC, ... with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 12 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0 010 0 010 00 01 011 000 01 011 0 011 0 011 000000 010 010 00 010 0 011 010 000 01 010 1 11 00 11 11 011 00000 011 00 011 010 00 011 010 0 011 0 010 1 010 1 010 10 011 011 000 01 01da00da01da 10 1a 11 da001a 010 a000a01da 11 da 11 da 10 da 11 da 10 da00da00daffffffff 11 1a001a 11 0a01da01da00da00da 10 0a01da 11 da 10 da 10 da 011 a 10 daffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffC,...

... destinationExample 1: RRNCF REG, 1, 0Before InstructionREG = 11 01 011 1After InstructionREG = 11 10 10 11 Example 2:RRNCF REG, 0, 0Before InstructionW=?REG = 11 01 011 1After InstructionW = 11 10 10 11 REG ... (00 01 1 010 )C=0After InstructionREG = 0x1B (00 01 1 011 )W = 0x00C =1 Z = 1 ; result is zeroN=0Example 3:SUBWFB REG, 1, 0Before InstructionREG = 0x03 (0000 0 011 )W = 0x0E (0000 11 01) C =1 After ... 0 011 2.37 2.47 2.57 VT ≥ 25°CLVV = 010 0 2.48 2.58 2.68 VLVV = 010 1 2.67 2.78 2.89 VLVV = 011 0 2.77 2.89 3. 01 VLVV = 011 1 2.98 3 .1 3.22 VLVV = 10 00 3.27 3. 41 3.55 VLVV = 10 01 3.47 3.61...

... MHz mode (1) 2(TOSC)(BRG + 1) —Note 1: Maximum pin capacitance = 10 pF for all I2C pins.Note: Refer to Figure 22-4 for load conditions.90 91 92 10 0 10 1 10 3 10 6 10 7 10 9 10 9 11 0 10 2SCLSDAInSDAOutPIC18FXX2DS39564C-page ... conditions.OSC1CLKOI/O Pin(input)I/O Pin(output)Q4Q1Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 Old ValueNew Value© 2006 Microchip Technology Inc. DS39564C-page 273PIC18FXX2TABLE 22-6: ... Conditions 10 TosH2ckL OSC1↑ to CLKO↓ —75200ns(Note 1) 11 TosH2ckH OSC1↑ to CLKO↑ —75200ns(Note 1) 12 TckR CLKO rise time — 35 10 0 ns (Note 1) 13 TckF CLKO fall time — 35 10 0 ns (Note 1) 14 TckL2ioV...