© 2006 Microchip Technology Inc. DS39564C-page 237 PIC18FXX2 MOVLW Move literal to W Syntax: [ label ] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → W Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal 'k' is loaded into W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process Data Write to W Example: MOVLW 0x5A After Instruction W = 0x5A MOVWF Move W to f Syntax: [ label ] MOVWF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) → f Status Affected: None Encoding: 0110 111a ffff ffff Description: Move data from W to register 'f'. Location 'f' can be anywhere in the 256 byte bank. If ‘a’ is 0, the Access Bank will be selected, over- riding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write register 'f' Example: MOVWF REG, 0 Before Instruction W = 0x4F REG = 0xFF After Instruction W = 0x4F REG = 0x4F PIC18FXX2 DS39564C-page 238 © 2006 Microchip Technology Inc. MULLW Multiply Literal with W Syntax: [ label ] MULLW k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: 0000 1101 kkkk kkkk Description: An unsigned multiplication is car- ried out between the contents of W and the 8-bit literal 'k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this opera- tion. A zero result is possible but not detected. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process Data Write registers PRODH: PRODL Example: MULLW 0xC4 Before Instruction W=0xE2 PRODH = ? PRODL = ? After Instruction W=0xE2 PRODH = 0xAD PRODL = 0x08 MULWF Multiply W with f Syntax: [ label ] MULWF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is car- ried out between the contents of W and the register file location 'f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and 'f' are unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this opera- tion. A zero result is possible but not detected. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W=0xC4 REG = 0xB5 PRODH = ? PRODL = ? After Instruction W=0xC4 REG = 0xB5 PRODH = 0x8A PRODL = 0x94 © 2006 Microchip Technology Inc. DS39564C-page 239 PIC18FXX2 NEGF Negate f Syntax: [ label ] NEGF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: ( f ) + 1 → f Status Affected: N, OV, C, DC, Z Encoding: 0110 110a ffff ffff Description: Location ‘f’ is negated using two’s complement. The result is placed in the data memory location 'f'. If ’a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write register 'f' Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [0x3A] After Instruction REG = 1100 0110 [0xC6] NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx Description: No operation. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None. PIC18FXX2 DS39564C-page 240 © 2006 Microchip Technology Inc. POP Pop Top of Return Stack Syntax: [ label ] POP Operands: None Operation: (TOS) → bit bucket Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previ- ous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation POP TOS value No operation Example: POP GOTO NEW Before Instruction TOS = 0031A2h Stack (1 level down) = 014332h After Instruction TOS = 014332h PC = NEW PUSH Push Top of Return Stack Syntax: [ label ] PUSH Operands: None Operation: (PC+2) → TOS Status Affected: None Encoding: 0000 0000 0000 0101 Description: The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows to implement a software stack by modifying TOS, and then push it onto the return stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode PUSH PC+2 onto return stack No operation No operation Example: PUSH Before Instruction TOS = 00345Ah PC = 000124h After Instruction PC = 000126h TOS = 000126h Stack (1 level down) = 00345Ah © 2006 Microchip Technology Inc. DS39564C-page 241 PIC18FXX2 RCALL Relative Call Syntax: [ label ] RCALL n Operands: -1024 ≤ n ≤ 1023 Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Status Affected: None Encoding: 1101 1nnn nnnn nnnn Description: Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2’s complement number ’2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'n' Push PC to stack Process Data Write to PC No operation No operation No operation No operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE+2) RESET Reset Syntax: [ label ] RESET Operands: None Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: All Encoding: 0000 0000 1111 1111 Description: This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start reset No operation No operation Example: RESET After Instruction Registers = Reset Value Flags* = Reset Value PIC18FXX2 DS39564C-page 242 © 2006 Microchip Technology Inc. RETFIE Return from Interrupt Syntax: [ label ] RETFIE [s] Operands: s ∈ [0,1] Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL, if s = 1 (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged. Status Affected: GIE/GIEH, PEIE/GIEL. Encoding: 0000 0000 0001 000s Description: Return from Interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If ‘s’ = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation pop PC from stack Set GIEH or GIEL No operation No operation No operation No operation Example: RETFIE 1 After Interrupt PC = TOS W=WS BSR = BSRS STATUS = STATUSS GIE/GIEH, PEIE/GIEL = 1 RETLW Return Literal to W Syntax: [ label ] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 1100 kkkk kkkk Description: W is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process Data pop PC from stack, Write to W No operation No operation No operation No operation Example: CALL TABLE ; W contains table ; offset value ; W now has ; table value : TABLE ADDWF PCL ; W = offset RETLW k0 ; Begin table RETLW k1 ; : : RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of kn © 2006 Microchip Technology Inc. DS39564C-page 243 PIC18FXX2 RETURN Return from Subroutine Syntax: [ label ] RETURN [s] Operands: s ∈ [0,1] Operation: (TOS) → PC, if s = 1 (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If ‘s’= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their cor- responding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data pop PC from stack No operation No operation No operation No operation Example: RETURN After Interrupt PC = TOS RLCF Rotate Left f through Carry Syntax: [ label ] RLCF f [,d [,a] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n+1>, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Encoding: 0011 01da ffff ffff Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is stored back in register 'f' (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write to destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C=0 After Instruction REG = 1110 0110 W = 1100 1100 C=1 C register f PIC18FXX2 DS39564C-page 244 © 2006 Microchip Technology Inc. RLNCF Rotate Left f (no carry) Syntax: [ label ] RLNCF f [,d [,a] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n+1>, (f<7>) → dest<0> Status Affected: N, Z Encoding: 0100 01da ffff ffff Description: The contents of register 'f' are rotated one bit to the left. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is stored back in register 'f' (default). If ’a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write to destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 After Instruction REG = 0101 0111 register f RRCF Rotate Right f through Carry Syntax: [ label ] RRCF f [,d [,a] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n-1>, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0011 00da ffff ffff Description: The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write to destination Example: RRCF REG, 0, 0 Before Instruction REG = 1110 0110 C=0 After Instruction REG = 1110 0110 W = 0111 0011 C=0 C register f © 2006 Microchip Technology Inc. DS39564C-page 245 PIC18FXX2 RRNCF Rotate Right f (no carry) Syntax: [ label ] RRNCF f [,d [,a] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n-1>, (f<0>) → dest<7> Status Affected: N, Z Encoding: 0100 00da ffff ffff Description: The contents of register 'f' are rotated one bit to the right. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If ’a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write to destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W=? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 register f SETF Set f Syntax: [ label ] SETF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: FFh → f Status Affected: None Encoding: 0110 100a ffff ffff Description: The contents of the specified regis- ter are set to FFh. If ’a’ is 0, the Access Bank will be selected, over- riding the BSR value. If ’a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write register 'f' Example: SETF REG,1 Before Instruction REG = 0x5A After Instruction REG = 0xFF PIC18FXX2 DS39564C-page 246 © 2006 Microchip Technology Inc. SLEEP Enter SLEEP mode Syntax: [ label ] SLEEP Operands: None Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO , 0 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0011 Description: The power-down status bit (PD) is cleared. The time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Go to sleep Example: SLEEP Before Instruction TO =? PD =? After Instruction TO =1 † PD =0 † If WDT causes wake-up, this bit is cleared. SUBFWB Subtract f from W with borrow Syntax: [ label ] SUBFWB f [,d [,a] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C ) → dest Status Affected: N, OV, C, DC, Z Encoding: 0101 01da ffff ffff Description: Subtract register 'f' and carry flag (borrow) from W (2’s complement method). If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored in register 'f' (default). If ’a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write to destination Example 1: SUBFWB REG, 1, 0 Before Instruction REG = 3 W=2 C=1 After Instruction REG = FF W=2 C=0 Z=0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W=5 C=1 After Instruction REG = 2 W=3 C=1 Z=0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W=2 C=0 After Instruction REG = 0 W=2 C=1 Z = 1 ; result is zero N=0 [...]... +85 °C FOSC = 32 kHz, VDD = 4.2V, -40°C to +125°C PIC18FXX2 D013 PIC18LFXX2 D013 PIC18FXX2 D014 PIC18LFXX2 D014 PIC18FXX2 IPD HS osc configuration FOSC = 4 MHz, VDD = 2.0V FOSC = 25 MHz, VDD = 5.5V HS + PLL osc configurations FOSC = 10 MHz, VDD = 5.5V Power-down Current(3) D020 PIC18LFXX2 — — — 08 1 3 9 4 10 μA μA μA VDD = 2.0V, +25°C VDD = 2.0V, -40°C to +85 °C VDD = 4.2V, -40°C to +85 °C D020 PIC18FXX2... Characteristic Min Typ Max Units Conditions 1. 98 2.06 2.14 V T ≥ 25°C 2. 18 2.27 2.36 V T ≥ 25°C 2.37 2.47 2.57 V T ≥ 25°C 2. 48 2. 58 2. 68 V LVV = 0101 2.67 2. 78 2 .89 V LVV = 0110 2.77 2 .89 3.01 V LVV = 0111 2. 98 3.1 3.22 V LVV = 1000 3.27 3.41 3.55 V LVV = 1001 3.47 3.61 3.75 V LVV = 1010 3.57 3.72 3 .87 V LVV = 1011 3.76 3.92 4. 08 V LVV = 1100 3.96 4.13 4.3 V LVV = 1101 4.16 4.33 4.5 V LVV = 1110 VLVD... Timer PIC18LFXX2 — — — 75 2 10 1.5 8 25 μA μA μA VDD = 2.0V, +25°C VDD = 2.0V, -40°C to +85 °C VDD = 4.2V, -40°C to +85 °C Watchdog Timer PIC18FXX2 — — — 7 10 25 15 25 40 μA μA μA VDD = 4.2V, +25°C VDD = 4.2V, -40°C to +85 °C VDD = 4.2V, -40°C to +125°C D022A ΔIBOR Brown-out Reset(5) PIC18LFXX2 — — — 29 29 33 35 45 50 μA μA μA VDD = 2.0V, +25°C VDD = 2.0V, -40°C to +85 °C VDD = 4.2V, -40°C to +85 °C D022A... disabled VDD = 2.0V, -40°C to +85 °C — — IDD Characteristic Conditions 40 50 70 100 μA μA LP osc, FOSC = 32 kHz, WDT disabled VDD = 4.2V, -40°C to +85 °C VDD = 4.2V, -40°C to +125°C Supply Current(2,4) D010 D010 D010A D010A PIC18LFXX2 PIC18FXX2 PIC18LFXX2 PIC18FXX2 XT osc configuration VDD = 2.0V, +25°C, FOSC = 4 MHz VDD = 2.0V, -40°C to +85 °C, FOSC = 4 MHz VDD = 4.2V, -40°C to +85 °C, FOSC = 4 MHz RC osc... PIC16C8X/ PIC16F8X ! ! ! PIC16F8XX MPLAB® ICE In-Circuit Emulator ! ! PIC16C9XX MPASMTM Assembler/ MPLINKTM Object Linker ! ! PIC17C4X ! ! PIC17C7XX ! ! MCRFXXX ! PIC12CXXX ! PIC18CXX2 MPLAB® C 18 C Compiler MPLAB® C17 C Compiler TABLE 21-1: Demo Boards and Eval Kits MPLAB® Integrated Development Environment PIC18FXX2 DEVELOPMENT TOOLS FROM MICROCHIP DS39564C-page 257 PIC18FXX2 NOTES: DS39564C-page 2 58. .. Technology Inc PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85 °C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85 °C for industrial... (Power-on Reset) for details V/ms See Section 3.1 (Power-on Reset) for details PIC18LFXX2 BORV1:BORV0 = 11 1. 98 — 2.14 V BORV1:BORV0 = 10 2.67 — 2 .89 BORV1:BORV0 = 01 4.16 — 4.5 V BORV1:BORV0 = 00 4.45 — 4 .83 V BORV1:BORV0 = 1x N.A — N.A V BORV1:BORV0 = 01 4.16 — 4.5 V BORV1:BORV0 = 00 4.45 — 4 .83 85 °C ≥ T ≥ 25°C V V D005 PIC18FXX2 Not in operating voltage range of device Legend: Shading of rows is to assist... DS39564C-page 263 PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85 °C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85 °C for industrial... DS39564C-page 261 PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85 °C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85 °C for industrial... Brown-out Reset(5) PIC18FXX2 — — — 36 36 36 40 50 65 μA μA μA VDD = 4.2V, +25°C VDD = 4.2V, -40°C to +85 °C VDD = 4.2V, -40°C to +125°C D022B ΔILVD Low Voltage Detect(5) PIC18LFXX2 — — — 29 29 33 35 45 50 μA μA μA VDD = 2.0V, +25°C VDD = 2.0V, -40°C to +85 °C VDD = 4.2V, -40°C to +85 °C D022B Low Voltage Detect(5) PIC18FXX2 — — — 33 33 33 40 50 65 μA μA μA VDD = 4.2V, +25°C VDD = 4.2V, -40°C to +85 °C VDD = 4.2V, . 0x34 TBLPTR = 0x01 389 A HOLDING REGISTER (0x01 389 A) = 0xFF HOLDING REGISTER (0x01 389 B) = 0xFF After Instruction (table write completion) TABLAT = 0x34 TBLPTR = 0x01 389 B HOLDING REGISTER (0x01 389 A) = 0xFF HOLDING. the 8 holding registers the TABLAT data is written to. The 8 holding registers are used to program the contents of Pro- gram Memory (P.M.). See Section 5.0 for information on writing to FLASH. MPLAB C17 and MPLAB C 18 C Compilers The MPLAB C17 and MPLAB C 18 Code Development Systems are complete ANSI ‘C’ compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers, respectively.