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Systems Design and Programming Basic I/O II CMPE 3101 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmable Peripheral Interface (82C55)The 82C55 is a popular interfacing component, that can interface any TTL-compatible I/O device to the microprocessor.It is used to interface to the keyboard and a parallel printer port in PCs (usu-ally as part of an integrated chipset).Requires insertion of wait states if used with a microprocessor using higherthat an 8 MHz clock.PPI has 24 pins for I/O that are programmable in groups of 12 pins and hasthree distinct modes of operation.In the PC, an 82C55 or its equivalent is decoded at I/O ports 60H-63H. Systems Design and Programming Basic I/O II CMPE 3102 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Pinout of 82C55 PPID1D2 D3D4D5D6D7D082C55RDWRA0A1CSRESETVCCGND A1 A0 Function 0 0 1 10101I/O Port AssignmentsPort A (PA7-PA0) and upperhalf of port C (PC7 - PC4)Group APort B (PB7-PB0) and lowerhalf of port C (PC3 - PC0)Group BPort APort BPort CCommand RegisterPA1PA2PA3PA4PA5PA6PA7PA0PB1PB2PB3PB4PB5PB6PB7PB0PC1PC2PC3PC4PC5PC6PC7PC0 Systems Design and Programming Basic I/O II CMPE 3103 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Interfacing the 82C55 PPIPort APort BPort CA7A3A4A6A5A0ABCG1G2AG2B0123456774ALS138IORCIOWCA1A2RESETD1D2D3D4D5D6D7D0PA1PA2PA3PA4PA5PA6PA7PA0PB1PB2PB3PB4PB5PB6PB7PB0PC1PC2PC3PC4PC5PC6PC7PC0RDWRA0A1CSRESETVCCGND82C55(C0H)(C2H)(C4H)(C6H)CommandRegister(Port addresses)D7--D08 Systems Design and Programming Basic I/O II CMPE 3104 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programming the 82C55Port C (PC3 - PC0)1 = input0 = outputPort B1 = input0 = outputMode0 = mode 01 = mode 1Mode00 = mode 001 = mode 11x = mode2Port A1 = input0 = outputPort C (PC7 - PC4)1 = input0 output17Command Byte ACommand Byte BBit set/reset1 = set0 = resetSelects a bit(Programs ports A, B, C)0Group BGroup A(Sets or resets any bits in port C)6 5 4 3 2 1 0x x x7 6 5 4 3 2 1 0 Systems Design and Programming Basic I/O II CMPE 3105 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 682C55: Mode 0 OperationD7--D082C55D0D7A0A7B7B0C7C0A0A1ResetIORCIOWC778-Digit Seven Segment LED Display InterfaceNCVccGnd16L8A4A5A6A8A9A7A10A12A14A15A13IO/MA11CSA0A1RDWRResetI1I10O1O8A3A28 Systems Design and Programming Basic I/O II CMPE 3106 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 682C55: Mode 0 OperationMode 0 operation causes the 82C55 to function as a buffered input device oras a latched output device.In previous example, both ports A and B are programmed as (mode 0) simplelatched output ports.Port A provides the segment data inputs to display and port B provides ameans of selecting one display position at a time.Different values are displayed in each digit via fast time multiplexing.The values for the resistors and the type of transistors used are determinedusing the current requirements (see text for details).Textbook has the assembly code fragment demonstrating its use.Examples of connecting LCD displays and stepper motors are also given. Systems Design and Programming Basic I/O II CMPE 3107 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 682C55: Mode 0 OperationD7-- D082C55D0D7A0A7B7B0C7C016L8A0A1A4A5A6A8A9A7A10A12A14A15A13IO/MA11CSResetIORCIOWCRow0Row1Row2Row3Col2Col1Col04x4 keyboard matrix interfaceCol3Vcc8RDWR Systems Design and Programming Basic I/O II CMPE 3108 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 682C55: Mode 0 OperationKEYScan KeysTime Delayfor de-bounceScan KeysCheckKeysIf key closedScan KeysTime Delayfor de-bounceScan KeysCheckKeysCalculatekey codeReturnIf key openFlow chart of a keyboard-scanning procedureWait for Release Wait for KeystrokeMomentaryglitch? Systems Design and Programming Basic I/O II CMPE 3109 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 682C55: Mode 1 Strobed InputPort A and/or port B function as latching input devices. External data isstored in the ports until the microprocessor is ready.Port C used for control or handshaking signals (cannot be used for data).Signal definitions for Mode 1 Strobed InputINTRInterrupt request is an output that requests an interruptIFBInput buffer full is an output indicating that the input latchcontain informationSTBThe strobe input loads data into the port latch on a 0-to-1 transitionINTEThe interrupt enable signal is neither an input nor an output; it is aninternal bit programmed via the PC4(port A) or PC2(port B) bits.PC7,PC6The port C pins 7 and 6 are general-purpose I/O pins that areavailable for any purpose. Systems Design and Programming Basic I/O II CMPE 31010 (Apr. 10, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 682C55: Mode 1 Strobed InputPC5PC4PC3IBFSTBINTRI/OINTEAPC6+7PORT AMode 1 Port APC1PC2PC0IBFSTBINTRINTEBPORT BMode 1 Port BSTBIBFINTRRDPort(Buffer full)(Interrupt request)Data strobedData read bymicroprocessorinto portTiming Diagram [...]... output indicating that the output buffer contains data for the bi-directional bus OBF UMBC 14 (Apr 10, 2002) PC2,PC1 Theses port C pins are general-purpose I/O pins that are and PC0 available for any purpose Interrupt request is an output that requests an interrupt INTR 82C55: Mode 2 Bi-directional Operation Only allowed with port A Bi-directional bused data used for interfacing two computers, GPIB... TI RE COUNT Y IVERSITY O F Basic I/O II CMPE 310 M Acknowledge is an input that enables tri-state buffers which are otherwise in their high-impedance state The strobe input loads data into the port A latch Input buffer full is an output indicating that the input latch contains information for the external bi-directional bus Interrupt enable are internal bits that enable the INTR pin Bit PC6(INTE1)...IVERSITY O F M 1966 DAV Keyboard D7 UMBC 11 (Apr 10, 2002) DAV is activated on a key press strobing the ASCII-coded key code into Port A YLAND BA L U M B C AR STB ASCII CMPE 310 Keyboard encoder debounces the key-switches, and provides a strobe whenever a key is depressed PC4 82C55 PA7 PA0 D0 Basic I/O II 82C55: Mode 1 Strobed Input Example Systems Design and... Programming MO UN TI RE COUNT Y IVERSITY O F M YLAND BA L 1966 U M B C AR STB OBF PC7 I/O PC5 PC 2-0 IBF PC4 ACK PC6 PORT A INTR CMPE 310 UMBC 15 (Apr 10, 2002) Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1 Strobed Output Timing diagrams INTE 2 INTE 1 PC3 Basic I/O II 82C55: Mode 2 Bi-directional Operation Systems Design and Programming MO UN TI RE COUNT Y ... input nor an output; it is an internal bit programmed via the PC6(port A) or PC2(port B) bits ACK INTR INTE M YLAND BA L 1966 U M B C AR UMBC 12 (Apr 10, 2002) PC5,PC4 The port C pins 5 and 4 are general-purpose I/O pins that are available for any purpose Output buffer full is an output that goes low when data is latched in either port A or port B Goes low on ACK OBF Signal Definitions for Mode 1 Strobed . 10101I/O Port AssignmentsPort A (PA7-PA0) and upperhalf of port C (PC7 - PC4)Group APort B (PB7-PB0) and lowerhalf of port C (PC3 - PC0)Group BPort APort BPort. MARYLAND BALTIMORE COUNTY1 9 6 682C55: Mode 0 OperationD 7-- D082C55D0D7A0A7B7B0C7C0A0A1ResetIORCIOWC778-Digit Seven Segment LED Display InterfaceNCVccGnd16L8A4A5A6A8A9A7A10A12A14A15A13IO/MA11CSA0A1RDWRResetI1I10O1O8A3A28 Systems