h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 53 Chapter 5 H8/300H Instructions and Addressing Mode Although programs were developed using simple instructions in Chapter 4, many other instructions are available for the H8/300H. In this chapter, all instructions for the H8/300H are listed in easy-to-understand tables. Some instructions frequently appear in programs while others are hardly used. At this stage, how to use each instruction is not described in detail. It does not matter if you do not understand some points. Detailed explanations are given in the next chapter, where sample programs are introduced. Since developing programs require frequent reference to the "instruction table", you should learn how to read the table at this stage. 5.1 Instructions Instruction types This section lists instructions provided in the H8/300H CPU. Not only instructions but all descriptions in this chapter are common to the entire H8/300H series including the H8/3048. Data transfer instructions Arithmetic instructions Logical instructions Conditional branch instructions Unconditional branch instructions Bit handling instructions Shift/Rotate instructions Block transfer instructions System control instructions - Data transfer instructions Instruction Meaning Description Sample program MOV MOVe data Data transfer PUSH PUSH data Stores data in the stack - POP POP data Restores data from the stack - - Arithmetic instructions Instruction Meaning Description Sample program ADD ADD binary Binary addition SUB SUBtract binary Binary subtraction - ADDX ADD with eXtend carry Binary addition with a carry - SUBX SUBtract with eXtend carry Binary subtraction with a carry - INC INCrement Increment DEC DECrement Decrement h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 54 ADDS ADD with Sign extension Binary address data addition SUBS SUBtract with Sign extension Binary address data subtraction - DAA Decimal Adjust Add Decimal adjustment (addition) - DAS Decimal Adjust Subtract Decimal adjustment (subtraction) - MULXU MULtiply eXtend as Unsigned Unsigned multiplication MULXS MULtiply eXtend as Signed Signed multiplication DIVXU DIVide eXtend as Unsigned Unsigned division DIVXS DIVide eXtend as Signed Signed division CMP CoMPare Comparison NEG NEGate Sign change - EXTS EXTend as Signed Signed extension - EXTU EXTend as Unsigned Unsigned extension - Logical instructions Instruction Meaning Description Sample program AND AND logical Logical product OR inclusive OR logical Logical sum XOR eXclusive OR logical Exclusive logical sum NOT NOT (logical complement) Logical negation - - Conditional branch instructions Instruction Meaning Description Sample program BHI Branch HIgh Branches if larger (unsigned) - BLS Branch Low or Same Branches if smaller or the same (unsigned) - BCC (BHS) Branch Carry Clear Branch High or Same Branches if no carry occurs (unsigned) BCS (BLO) Branch Carry Set Branch LOw Branches if a carry occurs (unsigned) - BNE Branch Not Equal Branches if not equal BEQ Branch EQual Branches if equal - BVC Branch oVerflow Clear Branches if no overflow occurs - BVS Branch oVerflow Set Branches if an overflow occurs - BPL Branch PLus Branches if positive - BMI Branch MInus Branches if negative - BGE Branch Greater or Equal Branches if larger or the same (signed) - BLT Branch Less Than Branches if smaller (signed) - BGT Branch Greater Than Branches if larger (signed) - BLE Branch Less or Equal Branches if smaller or the same (signed) - - Unconditional branch instructions Instruction Meaning Description Sample program JMP JuMP Unconditional jump - JSR Jump to SubRoutine Jumps to a subroutine BRA BRanch Always Unconditional branch h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 55 BSR Branch to SubRoutine Branches to a subroutine - RTS ReTurn from Subroutine Returns from a subroutine - Bit handling instructions Instruction Meaning Description Sample program BSET Bit SET Sets one bit BCLR Bit CLeaR Clears one bit BNOT Bit NOT Inverts one bit BTST Bit TeST 1-bit test BAND Bit AND 1-bit logical product - BIAND Bit Invert AND 1-bit inversion and logical product - BOR Bit inclusive OR 1-bit logical sum - BIOR Bit Invert OR 1-bit inversion and logical sum - BXOR Bit eXclusive OR Exclusive logical sum with one bit - BIXOR Bit Invert eXclusive OR 1-bit inversion and exclusive logical sum - BLD Bit LoaD Loads one bit (to a carry) - BILD Bit Invert LoaD Inverts and loads one bit (to a carry) - BST Bit STore Stores one bit (from a carry) - BIST Bit Invert STore Inverts and stores one bit (from a carry) - - Shift/Rotate instructions Instruction Meaning Description Sample program SHAL SHift Arithmetic Left Arithmetic left shift - SHAR SHift Arithmetic Right Arithmetic right shift - SHLL SHift Logical Left Logical left shift - SHLR SHift Logical Right Logical right shift - ROTL ROTate Left Left rotation - ROTR ROTate Right Right rotation - ROTXL ROTate with eXtend carry Left Left rotation with a carry - ROTXR ROTate with eXtend carry Right Right rotation with a carry - - Block transfer instructions Instruction Meaning Description Sample program EEPMOV MOVe data to EEPROM Data block transfer - * Serves as a data block transfer instruction since no EEPROM is provided with the H8/300H series. - System control instructions Instruction Meaning Description Sample program TRAPA TRAP Always Generates a trap - RTE ReTurn from Exception Returns from an exception handling routine - SLEEP SLEEP Sets the CPU in sleep state - LDC LoaD to Control register Loads data to the CCR - h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 56 STC STore from Control register Stores data from the CCR - ANDC AND Control register Logical product with the CCR - ORC inclusive OR Control register Logical sum with the CCR - XORC eXclusive OR Control register Exclusive logical sum with the CCR - NOP No OPeration No operation - 5.2 Addressing Modes As described in Chapter 4, most instructions consist of mnemonics and operands (targets for calculation or operation). Addressing modes represent how to specify targets for calculation or operation, in other words, how to write operands. There are nine addressing modes in all, each of which is selected according to whether the target is a general-purpose register or memory, and other factors. Some addressing modes are available only for specific instructions. Table 5.1: Addressing Mode Types Addressing mode Symbol Description Sample program Register direct Rn, En, ERn RnL, RnH Addressing for handling the contents of a general-purpose register. Immediate #xx Addressing for handling numeric values directly. Absolute address @aa Addressing for handling the contents of the memory. A memory address is directly written in an instruction. Register indirect @ERn Addressing for handling the contents of the memory. A memory address is represented by the contents of a general-purpose register. Register indirect with displacement @(disp,ERn) Addressing for handling the contents of the memory. A memory address is represented by the contents of a general-purpose register with displacement (distance) added. Post-increment register indirect @ERn+ Addressing for handling the contents of the memory. Although the contents of a general- purpose register is used as a memory h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 57 address, the contents are incremented after instruction execution. Predecrement register indirect @-ERn Addressing for handling the contents of the memory. Although the contents of a general- purpose register is used as a memory address, the contents are decremented before instruction execution. Memory indirect @@aa Addressing for branching by storing the destination address in the memory and specifying it. — Program counter relative Symbol Addressing for specifying a branch destination address. * n: General register number xx: Numeric value aa: Address disp: Displacement 5.3 Assembler Control Instructions The assembler control instructions are used to specify operation of the assembler when it converts a source program into an object program. Specifically, they instruct the assembler where a program starts and ends, how to reserve data or areas, and how to define symbols (no machine code is generated except for some data generation instructions). More than 30 assembler control instructions are available for the H8/300H series assembler. Among them, basic instructions are described in this section. For the assembler control instructions used in the sample programs in Chapter 6, check the specifications in the table below: Table 5.2: Assembler Control Instruction List Type Control instruction Functions 1.Section/ location .ALIGN Aligns an address to an even-numbered address or a 256-byte boundary. Put a boundary alignment number (2n) in the operand. Samples .ALIGN 2 ------------- (1) .DATA.W 1000 .ALIGN 256 ------------- (2) .DATA.W 2000 (1) Aligns an address to an even-numbered one. (2) Aligns an address to a 256-byte boundary. .SECTION Specifies start and resume of a section and declares the attribute. You can specify the name, attribute and start address of a section in the operand. Section attribute h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 58 CODE --- Code section DATA --- Data section Samples .SECTION SCT1,CODE,LOCATE=H'1000 --- (1) MOV.W R0,R1 MOV.W R2,R3 RTS .SECTION SCT2,DATA,LOCATE=H'2000 --- (2) ABC: .RES.W 1 (1) SCT1 specifies a code section and H'1000 as the start address. (2) SCT2 specifies a data section and H'2000 as the start address. .ORG Sets an address. Samples .SECTION SCT1,DATA,LOCATE=H'0000 DATA1: .DATA.W H'1234 .ORG H'0020 ------------- (1) DATA2: .DATA.W H'5678 .ORG H'0040 ------------- (2) DATA3: .DATA.W H'ABCD (1) Sets an address to H'0020. DATA2 is allocated to the H'0020 address. (2) Sets an address to H'0040. DATA3 is allocated to the H'0040 address. 2.Setting of symbol value .EQU Sets a value for a symbol. 3.Setting of data .DATA Reserves integer data based on the specified size. Following ".", B (Byte), W (Word) or L (Long word) can be specified as the size of the data to be set. Unless specified, "W" is assumed. Put integer data to be set in the operand. You can specify multiple integer data blocks using "," as a separator. The symbol represents the start address of the reserved data. .SDATA Reserves string data. Specify the string to be reserved in the operand. Characters must be enclosed with "". You can specify up to 255 characters. The symbol represents the start address of the reserved string data. 4.Reservation of data area .RES Reserves an integer data area based on the specified size. Following ".", B (Byte), W (Word) or L (Long word) can be specified as the size of the area to be reserved. Unless specified, "W" is assumed. Put the count of areas to be reserved in the operand. The symbol represents the start address of the reserved area. 5.Specification of CPU .CPU Specifies the target CPU for the source program to be assembled. The H8/300H CPU types are as follows: h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 59 300HA:20 ------ Operates in a 1Mbyte memory space 300HA:24 ------ Operates in a 16Mbyte memory space (":24" may be omitted) 6. Other .END Indicates the end of a source program. Put this instruction in the end of a source program. If part of a source program continues following this instruction, it is ignored and not assembled. 5.4 How to Read the Instruction Table This section describes how to read the instruction table detailing each instruction. The instructions described in 5.1 have specific data size and addressing mode they can execute, and how each flag in the CCR changes after execution differs. These detailed instruction specifications are described in the instruction table. The following shows how to read it. Execution state count "Execution state count" is synonymous with "execution clock count". For example, if the system clock executes the following at 10MHz (1 clock = 0.1 microsecond): MOV.B #xx,Rd (execution state count = 2) Execution takes 0.2 microsecond. Example for referring to the execution state count Next, when execution states are referred to is described using an example. Example: There are three ways to clear a general-purpose register to zero: (1) MOV.B #0,R0L Transfers zero (2) SUB.B R0L,R0L Subtracts itself (3) XOR.B R0L,R0L Executes the exclusive logical sum with itself h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 60 If the data size is byte as shown above, the execution state count is 2 for all of the three. This means that there is no difference in speed. If the data size is long word (32 bit), however, the counts change as follows: Execution state count (1) MOV.L #0,ER0 6 (2) SUB.L ER0,ER0 2 (3) XOR.L ER0,ER0 4 From the above, you can see that SUB.L ER0,ER0 has the shortest execution time. When the same process can be achieved with several methods as shown above, you should check their execution state counts (and instruction lengths) to select the one with the smallest count. 1. Point out the errors in the following instructions. (Some instructions, however, may not include errors.) (1) MOV.B #H'FF,@RESULT (2) MOV.B #H'FF,@ER0+ (3) MOV.B @-ER0,R1L (4) CMP.B R0L,#0 (5) MOV.B R0,R1 (6) MOV.B #200,R0L (7) MOV.B #500,R0L (8) ADD.B @DATA,R0L Answers (1) The MOV instruction cannot transfer immediate data directly to the memory. (2) Post-increment register indirect can only be specified for the source operand. (3) Predecrement register indirect can only be specified for the destination operand. (4) Immediate data can only be specified for the source operand. (5) The specified data size is wrong. Since the R0 and R1 are 16-bit general- purpose registers, the data size must be "W". (6) Correct. (7) A decimal number of "500" cannot be handled when the size is byte (8 bits). (8) The ADD instruction cannot directly calculate data in the memory. 2. After the following instruction is executed, by how many will the value of the ER0 be decremented from that before execution. MOV.B R1H,@-ER0 h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 61 Answer: 1 One is subtracted when the size of the data to be transferred is byte. 3. All of the following instructions clear the ER0 to zero. Which has the shortest length? (1) MOV.L #0,ER0 (2) SUB.L ER0,ER0 (3) XOR.L ER0,ER0 Answer: (2) (1) is 6-byte long. (2) is 2-byte long. (3) is 4-byte long. So, (2) SUB.L ER0,ER0 is the shortest. 4. List advantage and disadvantage of single-chip microcomputers, one for each. Advantage (Small, inexpensive) Disadvantage (Limited internal functions) (Small memory capacity, unsuitable for large-scale systems) Since single-chip microcomputers have all functions on one chip, they are small and less expensive than buying components separately. Circuit integration, however, is limited and thus cannot accommodate relatively large memory. . transfer instructions Arithmetic instructions Logical instructions Conditional branch instructions Unconditional branch instructions Bit handling instructions. 5.2 Addressing Modes As described in Chapter 4, most instructions consist of mnemonics and operands (targets for calculation or operation). Addressing modes