ABSTRACT USB (Universal Serial Bus) interface has many applications in computer communication because it can transfer the data in high speed The aim for this work has been to develop a USB interface that it can transfer data to and from FPGA and computer via an EZ-USB FX2PL microcontroller from Cypress semiconductor The work is intended to be used in nuclear instrumentation development at Nuclear Physics Department, Faculty of Physics and Engineering Physics, University of Science HCMC The development is designed to be used to replace the RS-232 interface in some nuclear electronic devices which have the connection with computer in order to increase the transfer rate An EXK board is used as a reference hardware that includes an FPGA Spartan-3E from Xilinx and an EZ-USB FX2LP microcontroller The microcontroller was chosen because it is a high-speed USB microcontroller We develop the firmware for Cypress chip by C-language and using VHDL to implement for FPGA To show the data on the screen, a user interface is developed by visual C# The thesis is arranged with chapters: Chapter 1: Introduce the purpose and the main components of this work Chapter 2: Introduce the hardware design Chapter 3: Introduce the software design Chapter 4: Results and Discussion The conclusion gives summary of results In future work section, some proposals to improve the system are suggested This section also discusses its applications for the near future In appendix A, you can find some VHDL codes for FPGA Xilinx Appendix B provides firmware used to control the Cypress Chip i By student, Academic year 2006-2010 Nguyen Vo Bao Ngan (E-mail address: bao2005ngan@yahoo.com) ii Tóm tắt PHÁT TRIỂN GIAO TIẾP USB SỬ DỤNG VI ĐIỀU KHIỂN CYPRESS EZ-USB FX2LP VÀ CÔNG NGHỆ FPGA Nguyễn Võ Bảo Ngân MSSV: 0613068 bao2005ngan@yahoo.com Sinh viên khóa 2006-2010 Bộ môn Vật lý Điện tử, Khoa Vật lý Vật lý Kỹ thuật Trường Đại học Khoa học Tự Nhiên, ĐHQG Tp.Hồ Chí Minh Tiến sĩ Võ Hồng Hải Bộ môn vật lý hạt nhân vhhai@phys.hcmuns.edu.vn Ngày USB trở nên phổ biến, chúng xuất hầu hết thiết bị điện tử chuột, bàn phím, máy in, điện thoại…USB có khả truyền liệu tốc độ cao kết nối thiết bị với máy tính mà khơng phải khởi động máy tính lại Chính ưu điểm USB, phát giao tiếp USB để thay cho chuẩn RS-232 thiết bị đo lường môn vật lý hạt nhân nói riêng cho thiết bị cần truyền liệu tốc độ cao Đề thực với phần cứng thiết kế nhóm cựu sinh viên Học Viện Kỹ Thuật Quân Sự Hà Nội Phần cứng cho phép truyền liệu máy tính FPGA Xilinx Spartan-3E thơng qua chip USB Cypress Cy7C68013A Dòng Cypress chip hỗ trợ truyền chế độ ‘full speed’ ‘high speed’.Để phần cứng hoạt động viết firmware để cấu hình chip Cypress lập trình phần cứng cho FPGA Xilinx ngôn ngữ VHDL Đồng thời tạo giao diện để thị kết lên máy tính Visual C# Kết mạch hoạt động ổn định chế độ ‘full speed’, truyền liệu ổn định từ FPGA lên máy tính hiến thị lên giao diện tạo Từ kết đạt chúng tối tiếp tục phát triền phần cứng phần mềm để mạch hoạt động chế độ ‘high speed” nhầm nâng cao tốc độ truyền liệu Sau đó, chúng tơi sử dụng chip Cypress để thiết kế giao tiếp USB thiết bị thu nhận liệu FlashADCFPGA ( phát triển cho nghiên cứu hạt nhân đại học Osaka Nhật Bản) iii ACKNOWLEDGMENTS This thesis would not have been possible without the help of a number of people, and I would like to express my gratitude to all of them Professor NOMACHI MASAHARU of Osaka University helped me with FPGA development kits Dr VO HONG HAI of Department of nuclear physics helps me a lot during doing this thesis at nuclear physics Lab Thanks to Dr NGUYEN VAN HIEU and all other teachers for your help during the study at University of Science Thanks to my friends and my family for your advices during writing the thesis HoChiMinh City, July / 2010 Nguyen Vo Bao Ngan iv Comments by Supervisor Ho Chi Minh City, July 2010 Dr Vo Hong Hai v Comment by Reviser Ho Chi Minh City, July 2010 BSc Truong Thien Dinh vi Table of contents Abstract…….……………………………………………………………………… i Tóm tắt .iii Acknowledgements iv Comments by supervisor v Comment by reviser vi Table of contents vii List of abbreviation ix List of figure x List of table xii CHAPTER I INTRODUCTION I.1 Purpose I.2 USB ( Universal Serial Bus) I.3 FPGA I.4 The main components .2 CHAPTER II HARDWARE .4 II.1 Cypress EZ-USB FX2LP Microcontroller (CY7C68013A) II.2 Xilinx Spartan-3E .10 III.3 Large EEPROM ATMEL 24C64A 12 CHAPTER III SOFTWARE .13 III.1 Development Environment .13 III.2 Firmware 13 III.2.1 Firmware for Cypress 13 III.2.2 Firmware for FPGA 17 III.3 EEPROM image .20 III.4 Drivers 21 III.5 User interface 22 CHAPTER IV RESULTS AND DISCUSSION .24 Conclusion 25 Future work 26 References 27 Appendix A VHDL CODE 28 Appendix B Firmware for Cypress 37 vii List of Abbreviations USB Universal Serial Bus MCU Micro Controller Unit viii CPU Complex Programmable Logic Device FIFO First In First Out VHDL Very high speed integrated circuit Hardware Description Language EEPROM Electrically Erasable Programmable Read Only Memory FPGA Field Programmable Gate Arrays PCB Printed Circuit Board VID Vendor ID PID Product ID DID Device ID (queue) LIST OF FIGURES Figure 1.1 Computer and EXF board connection Figure 2.1 EXK board Figure 2.2 Cypress module Figure 2.3 FPGA module .5 ix Figure 2.4 Cypress CY7C68013A Figure 2.5 EZ-USB Endpoint buffer Figure 2.6 EZ-USB FX2LP architecture Figure 2.7 Connection between EZ-USB and FPGA Xilinx Figure 2.8 Simplified example of a general FPGA logic architecture 12 Figure 2.9 EEPROM ATMEL 12 Figure 3.1 Firmware project 17 Figure 3.2 Interface Pins Example: Asynchronous FIFO Writes 18 Figure 3.3 Asynchronous FIFO Writes State Machine 19 Figure 3.4 Interface Pins Example: Asynchronous FIFO Reads 19 Figure 3.5 Asynchronous FIFO Reads State Machine 20 Figure 3.6 hex2bix command 21 Figure 3.7 Windriver interface .22 Figure 3.8 User interface using Visual Studio Net .23 Figure 4.1: Receiving data from FPGA .24 x Firmware for Cypress CY7C68013A #pragma NOIV // Do not generate interrupt vectors // // File: bulksrc.c // Contents: Hooks required to implement USB peripheral function // // $Archive: /USB/Examples/Fx2/bulksrc/bulksrc.c $ // $Date: 11/10/01 11:41a $ // $Revision: $ // // Copyright (c) 2000 Cypress Semiconductor All rights reserved // #include "fx2.h" #include "fx2regs.h" #include "fx2sdly.h" // SYNCDELAY macro extern BOOL GotSUD; // Received setup data flag extern BOOL Sleep; extern BOOL Rwuen; extern BOOL Selfpwr; BYTE Configuration; // Current configuration BYTE AlternateSetting; // Alternate settings BYTE xdata myBuffer[512]; WORD myBufferCount; 37 // // Task Dispatcher hooks // The following hooks are called by the task dispatcher // - void TD_Init(void) // Called once at startup { REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to SYNCDELAY; FIFORESET = 0x80; // reset all FIFOs SYNCDELAY; FIFORESET = 0x02; SYNCDELAY; FIFORESET = 0x04; SYNCDELAY; FIFORESET = 0x06; SYNCDELAY; FIFORESET = 0x08; SYNCDELAY; FIFORESET = 0x00; SYNCDELAY; // this defines the external interface to be the following: IFCONFIG = 0xCB; // use IFCLK pin driven by external logic (5MHz to 48MHz) 38 // use slave FIFO interface pins driven sync by external master EP6FIFOCFG = 0x0C; // this lets the FX2 auto commit IN packets, gives the // ability to send zero length packets, // and sets the slave FIFO data interface to 8-bits SYNCDELAY; EP6CFG = 0xE2; // sets EP8 valid for IN's SYNCDELAY; // and defines the endpoint for 512 byte packets, 2x buffered EP2CFG = 0xA2; FIFORESET = 0x80; // Reset the FIFO SYNCDELAY; FIFORESET = 0x02; SYNCDELAY; FIFORESET = 0x00; SYNCDELAY; EP2FIFOCFG = 0x00; // EP2 is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=0 SYNCDELAY; SYNCDELAY; // out endpoints not POR (power-on reset) armed EP2BCL = 0x80; // since the defaults are double buffered we must SYNCDELAY; // write dummy byte counts twice EP2BCL = 0x80; w/skip // arm EP2OUT & EP4OUT by writing to the byte count SYNCDELAY; 39 PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0] SYNCDELAY; // FLAGB as full flag, as pointed to by FIFOADR[1:0] PINFLAGSCD = 0x08; // FLAGC as empty flag, as pointed to by FIFOADR[1:0] // won't generally need FLAGD PORTACFG = 0x00; // used PA7/FLAGD as a port pin, not as a FIFO flag FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low SYNCDELAY; EP6AUTOINLENH = 0x00; // you can define these as you wish, SYNCDELAY; // to have the FX2 automatically limit IN's EP6AUTOINLENL = 0x40; SYNCDELAY; EP8FIFOPFH = 0x82; // you can define the programmable flag (FLAGA) SYNCDELAY; // to be active at the level you wish EP8FIFOPFL = 0x00; SYNCDELAY; // out endpoints not POR (power-on reset) armed EP4BCL = 0x80; SYNCDELAY; EP4BCL = 0x80; // enable dual autopointer(s) 40 AUTOPTRSETUP |= 0x01; Rwuen = TRUE; // Enable remote-wakeup } void TD_Poll(void) // Called repeatedly while the device is idle { if( !( EP2468STAT & 0x01 ) ) { // EP2EF=0 when FIFO NOT empty, host sent packet OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master } } BOOL TD_Suspend(void) // Called before the device goes into suspend mode { return(TRUE); } BOOL TD_Resume(void) // Called after the device resumes { return(TRUE); } 41 // // Device Request hooks // The following hooks are called by the end point device request parser // - BOOL DR_GetDescriptor(void) { return(TRUE); } BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received { Configuration = SETUPDAT[2]; return(TRUE); // Handled by user code } BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received { EP0BUF[0] = Configuration; EP0BCH = 0; EP0BCL = 1; return(TRUE); // Handled by user code } 42 BOOL DR_SetInterface(void) received // Called when a Set Interface command is { AlternateSetting = SETUPDAT[2]; return(TRUE); // Handled by user code } BOOL DR_GetInterface(void) received // Called when a Set Interface command is { EP0BUF[0] = AlternateSetting; EP0BCH = 0; EP0BCL = 1; return(TRUE); // Handled by user code } BOOL DR_GetStatus(void) { return(TRUE); } BOOL DR_ClearFeature(void) { return(TRUE); 43 } BOOL DR_SetFeature(void) { return(TRUE); } BOOL DR_VendorCmnd(void) { return(TRUE); } // // USB Interrupt Handlers // The following functions are called by the USB interrupt jump table // - // Setup Data Available Interrupt Handler void ISR_Sudav(void) interrupt { GotSUD = TRUE; // Set flag EZUSB_IRQ_CLEAR(); USBIRQ = bmSUDAV; // Clear SUDAV IRQ } 44 // Setup Token Interrupt Handler void ISR_Sutok(void) interrupt { EZUSB_IRQ_CLEAR(); USBIRQ = bmSUTOK; // Clear SUTOK IRQ } void ISR_Sof(void) interrupt { EZUSB_IRQ_CLEAR(); USBIRQ = bmSOF; // Clear SOF IRQ } void ISR_Ures(void) interrupt { if (EZUSB_HIGHSPEED()) { pConfigDscr = pHighSpeedConfigDscr; pOtherConfigDscr = pFullSpeedConfigDscr; } else { pConfigDscr = pFullSpeedConfigDscr; pOtherConfigDscr = pHighSpeedConfigDscr; } 45 EZUSB_IRQ_CLEAR(); USBIRQ = bmURES; // Clear URES IRQ } void ISR_Susp(void) interrupt { Sleep = TRUE; EZUSB_IRQ_CLEAR(); USBIRQ = bmSUSP; } void ISR_Highspeed(void) interrupt { if (EZUSB_HIGHSPEED()) { pConfigDscr = pHighSpeedConfigDscr; pOtherConfigDscr = pFullSpeedConfigDscr; } else { pConfigDscr = pFullSpeedConfigDscr; pOtherConfigDscr = pHighSpeedConfigDscr; } 46 EZUSB_IRQ_CLEAR(); USBIRQ = bmHSGRANT; } void ISR_Ep0ack(void) interrupt { } void ISR_Stub(void) interrupt { } void ISR_Ep0in(void) interrupt { } void ISR_Ep0out(void) interrupt { } void ISR_Ep1in(void) interrupt { } void ISR_Ep1out(void) interrupt { } void ISR_Ep2inout(void) interrupt { } void ISR_Ep4inout(void) interrupt 47 { } void ISR_Ep6inout(void) interrupt { } void ISR_Ep8inout(void) interrupt { } void ISR_Ibn(void) interrupt { } void ISR_Ep0pingnak(void) interrupt { } void ISR_Ep1pingnak(void) interrupt { } void ISR_Ep2pingnak(void) interrupt { } void ISR_Ep4pingnak(void) interrupt { } void ISR_Ep6pingnak(void) interrupt { 48 } void ISR_Ep8pingnak(void) interrupt { } void ISR_Errorlimit(void) interrupt { } void ISR_Ep2piderror(void) interrupt { } void ISR_Ep4piderror(void) interrupt { } void ISR_Ep6piderror(void) interrupt { } void ISR_Ep8piderror(void) interrupt { } void ISR_Ep2pflag(void) interrupt { } void ISR_Ep4pflag(void) interrupt { } 49 void ISR_Ep6pflag(void) interrupt { } void ISR_Ep8pflag(void) interrupt { } void ISR_Ep2eflag(void) interrupt { } void ISR_Ep4eflag(void) interrupt { } void ISR_Ep6eflag(void) interrupt { } void ISR_Ep8eflag(void) interrupt { } void ISR_Ep2fflag(void) interrupt { } void ISR_Ep4fflag(void) interrupt { } void ISR_Ep6fflag(void) interrupt 50 { } void ISR_Ep8fflag(void) interrupt { } void ISR_GpifComplete(void) interrupt { } void ISR_GpifWaveform(void) interrupt { } 51 ... bao2005ngan@yahoo.com) ii Tóm tắt PHÁT TRIỂN GIAO TIẾP USB SỬ DỤNG VI ĐIỀU KHIỂN CYPRESS EZ -USB FX2LP VÀ CÔNG NGHỆ FPGA Nguyễn Võ Bảo Ngân MSSV: 0613068 bao2005ngan@yahoo.com Sinh vi n khóa 2006-2010 Bộ... điểm USB, phát giao tiếp USB để thay cho chuẩn RS-232 thiết bị đo lường mơn vật lý hạt nhân nói riêng cho thiết bị cần truyền liệu tốc độ cao Đề thực với phần cứng thiết kế nhóm cựu sinh vi n... and accelerates USB peripheral development using the EZ -USB chip The FrameWorks implements 8051 code for EZ -USB chip initialization, USB standard device request handling, and USB suspend power