Springer functional verification of programmable embedded architectures a top down approach (springer)

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Functional Verification of Programmable Embedded Architectures A Top-Down Approach FUNCTIONAL VERIFICATION OF PROGRAMMABLE EMBEDDED ARCHITECTURES A Top-Down Approach PRABHAT MISHRA Department of Computer and Information Science and Engineering University of Florida, USA NIKIL D DUTT Center for Embedded Computer Systems Donald Bren School of Information and Computer Sciences University of California, Irvine, USA 4y Springer Prabhat Mishra University of Florida USA Nikil D Dutt University of California, Irvine USA Functional Verification of Programmable Embedded Architectures A Top-Down Approach ISBN 0-387-26143-5 ISBN 978-0387-26143-0 e-ISBN 0-387-26399-3 Printed on acid-free paper © 2005 Springer Science+Business Media, Inc All rights reserved This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, Inc., 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights Printed in the United States of America springeronline.com SPIN 11430100 To our families Contents Preface xv Acknowledgments xix I Introduction to Functional Verification Introduction 1.1 Motivation 1.1.1 Growth of Design Complexity 1.1.2 Functional Verification - A Challenge 1.2 Traditional Validation Flow 1.3 Top-Down Validation Methodology 1.4 Book Organization II Architecture Specification Architecture Specification 2.1 Architecture Description Languages 2.1.1 Behavioral ADLs 2.1.2 Structural ADLs 2.1.3 Mixed ADLs 2.1.4 Partial ADLs 2.2 ADLs and Other Specification Languages 2.3 Specification using EXPRESSION ADL 2.3.1 Processor Specification 2.3.2 Coprocessor Specification 2.3.3 Memory Subsystem Specification 2.4 Chapter Summary 3 10 12 13 15 16 18 19 19 20 20 21 24 25 27 28 viii III CONTENTS Validation of Specification 3.1 Validation of Static Behavior 3.1.1 Graph-based Modeling of Pipelines 3.1.2 Validation of Pipeline Specifications 3.1.3 Experiments 3.2 Validation of Dynamic Behavior 3.2.1 FSM-based Modeling of Processor Pipelines 3.2.2 Validation of Dynamic Properties 3.2.3 A Case Study 3.3 Related Work 3.4 Chapter Summary Top-Down Validation 29 30 31 34 45 48 48 54 59 61 62 63 Executable Model Generation 4.1 Survey of Contemporary Architectures 4.1.1 Summary of Architectures Studied 4.1.2 Similarities and Differences 4.2 Functional Abstraction 4.2.1 Structure of a Generic Processor 4.2.2 Behavior of a Generic Processor 4.2.3 Structure of a Generic Memory Subsystem 4.2.4 Generic Controller 4.2.5 Interrupts and Exceptions 4.3 Reference Model Generation 4.4 Related Work 4.5 Chapter Summary 65 66 66 68 69 69 73 74 74 75 77 80 81 Design Validation 5.1 Property Checking using Symbolic Simulation 5.2 Equivalence Checking 5.3 Experiments 5.3.1 Property Checking of a Memory Management Unit 5.3.2 Equivalence Checking of the DLX Architecture 5.4 Related Work 5.5 Chapter Summary 83 85 87 88 88 91 92 93 CONTENTS ix Functional Test Generation 6.1 Test Generation using Model Checking 6.1.1 Test Generation Methodology 6.1.2 A Case Study 6.2 Functional Coverage driven Test Generation 6.2.1 Functional Fault Models 6.2.2 Functional Coverage Estimation 6.2.3 Test Generation Techniques 6.2.4 A Case Study 6.3 Related Work 6.4 Chapter Summary 95 95 96 99 103 103 105 106 112 116 117 IV 119 V Future Directions Conclusions 7.1 Research Contributions 7.2 Future Directions Appendices 121 121 122 125 A Survey of Contemporary ADLs A.I Structural ADLs A.2 Behavioral ADLs A.3 Mixed ADLs A.4 Partial ADLs 127 127 130 134 139 B Specification of DLX Processor 141 C Interrupts & Exceptions in ADL 147 D Validation of DLX Specification 151 E Design Space Exploration E.I Simulator Generation and Exploration 155 156 E.2 Hardware Generation and Exploration 162 References 167 Index 179 List of Figures 1.1 1.2 1.3 1.4 1.5 1.6 1.7 An example embedded system Exponential growth of number of transistors per integrated circuit North America re-spin statistics Complexity matters Pre-silicon logic bugs per generation Traditional validation flow Proposed specification-driven validation methodology 11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 ADL-driven exploration and validation of programmable architectures Taxonomy of ADLs Commonality between ADLs and non-ADLs Block level description of an example architecture Pipeline level description of the DLX processor shown in Figure 2.4 Specification of the processor structure using EXPRESSION ADL Specification of the processor behavior using EXPRESSION ADL Coprocessor specification using EXPRESSION ADL Memory subsystem specification using EXPRESSION ADL 16 17 21 22 23 24 25 26 27 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Validation of pipeline specifications An example architecture A fragment of the behavior graph An example processor with false pipeline paths An example processor with false data-transfer paths The DLX architecture ADL driven validation of pipeline specifications A fragment of a processor pipeline The processor pipeline with only instruction registers Automatic validation framework using SMV 30 32 33 36 37 46 49 50 51 59 xii LIST OF FIGURES 3.11 Automatic validation framework using equation solver 60 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 A fetch unit example Modeling of RenameRegister function using sub-functions Modeling of MAC operation Modeling of associative cache function using sub-functions Example of distributed control Example of centralized control Mapping between MACcc and generic instructions Simulation model generation for the DLX architecture 70 72 73 74 75 76 78 79 5.1 5.2 5.3 84 85 5.4 Top-down validation methodology Test vectors for validation of an AND gate Compare point matching between reference and implementation design TLB block diagram 6.1 6.2 6.3 6.4 Test program generation methodology A fragment of the DLX architecture Test Generation and Coverage Estimation Validation of the Implementation 97 100 112 114 C.I C.2 C.3 C.4 Specification Specification Specification Specification 148 148 149 149 D.I The DLX processor with pipeline registers of division_by_zero exception of illegaLslot_instruction exception of machine_reset exception of interrupts E.I Architecture exploration framework E.2 Cycle counts for different graduation styles E.3 Functional unit versus coprocessor E.4 Cycle counts for the memory configurations E.5 The application program E.6 Pipeline path exploration E.7 Pipeline stage exploration E.8 Instruction-set exploration 87 89 152 156 158 160 162 163 164 165 166 .. .Functional Verification of Programmable Embedded Architectures A Top- Down Approach FUNCTIONAL VERIFICATION OF PROGRAMMABLE EMBEDDED ARCHITECTURES A Top- Down Approach PRABHAT MISHRA Department... Grun, Ashok Halambi, Arun Kejariwal, Dr Narayanan Krishnamurthy, Dr Mahesh Mamidipaka, Prof Alex Nicolau, Dr Frederic Rousseau, Prof Sandeep Shukla, and Prof Hiroyuki Tomiyama We are also thankful... the challenges in functional verification of programmable architectures, and relating a traditional bottom-up validation approach against our proposed top- down validation methodology Chapter
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