Springer cmos logic circuit design

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!!!!൞䶂‫ࢬڇ‬吨再ऱ㪤‫ء‬䶣՗֮䱀‫ط‬FQVCDO!HSPVQࠫ‫נ܂‬঴Ζ !!!!‫ء‬䢰ठ䰏㢖‫ڶࢬृ܂‬ΔFQVCDO!HSPVQ‫׽‬೚ᖞ෻Εࠫ‫܂‬Ε᫪伵䦡ؒՠ‫܂‬Ζ‫ڇ‬অ兓ᄭ֮䱀㡕୲‫ݙ‬ᖞΕ࿴ 㨕ऱൣ㤝ՀΔ൞‫אױ‬㢑‫֮ء‬䱀劓۩剖剧Ζ‫࣠ڕ‬൞ኩრΔ冉‫ڇ‬剖剧ऱ㦍ଢ㡹Ղ‫ݺ‬䣙ऱ᫪伵劖൷Δ㪤Ոਢ㢑 ‫ݺ‬䣙ՠ‫܂‬ऱ༇ૹΖ !!!!‫࣠ڕ‬൞Ꮑ૞ࠌ‫֮ءش‬䱀խऱຝ։ࢨृ٤ຝ㡕୲Δ‫شא‬ՊਬẊ೸䢓‫ش‬ຜΔ冉侶ߓ֮䱀‫ृ܂‬Δ‫࢔ڇ‬൓‫܂‬ ृ‫ٵ‬რ൓ൣ㤝ՀΔ൞‫אױ‬佀但൞ऱ۩䢠Ζ‫࣠ڕ܀‬൞㦠‫࢔ڶ‬൓‫ٵृ܂‬რۖᖐ۞‫ش‬ՊਬẊ೸䢓ࢨॺ೸䢓‫ؾ‬ऱ ΔFQVCDO!HSPVQ㰒լ㢑‫ڼ‬凔ٚ۶凘ٚΖ !!!!‫࣠ڕ‬൞‫ڶ‬რ‫ڇ‬᫪伵Ղ‫נ‬ठ൞ऱ‫܂‬঴Δࢨृ൞‫ړ܂ࠫڶ‬ऱ‫׊‬伨㧄඄䰏䣠ᐾऱ‫܂‬঴Δ‫ݺ‬䣙ॺൄ㣴०൞ٌ ղ‫ݺ‬䣙䢠൞‫܍‬凮䣠ᐾࡉ䦡ؒΔ侶伵ॾᒣਢΚfqvcdoAnto/dpnΖ !!!!㣴०兑向‫ݺ‬䣙ऱ᫪ీΜຏ㧄᫪ీΔ൞‫אױ‬㸀൓‫܍ڍޓ‬凮凹允ᩓՀ剧Ζ‫ݺ‬䣙ऱ᫪ీ‫ܿچ‬ਢΚ iuuq;00xxx/fqvcdo/dpnΖ !!!!㣴०‫ף‬Ե‫ݺ‬䣙ऱ兌䨫Μຏ㧄兌䨫Δ൞㰒‫ף‬ԵFQVCDO!HSPVQՕ୮அΔ伬兘‫ڍޓ‬ऱ‫ٵݳ‬ሐ‫ٽ‬ऱ֖ࣛΔ‫ڢ‬ ᩓ‫ה‬䣙։ࠆ凹ᄭΜ‫ݺ‬䣙ऱ兌䨫‫ܿچ‬ਢΚiuuq;00xxx/fqvcdo/pshΖ !!!!‫࣠ڕ‬൞‫ڶ‬ٚ۶ጊ向ࢨृრ儁Ε৬兀Δ冉൞ᩓ‫ݺ‬䣙侶伵Ζ侶伵ॾᒣΚfqvcdoAnto/dpnΖ !!!!່‫ٿ‬Δ٦‫ڻ‬ტ冴൞Հ剧‫ڢ‬吨再‫ط‬FQVCDO!HSPVQࠫ‫נ܂‬঴ऱ䶣՗‫נ‬ठढΖ CMOS LOGIC CIRCUIT DESIGN This Page Intentionally Left Blank CMOS LOGIC CIRCUIT DESIGN John P Uyemura Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW eBook ISBN: Print ISBN: 0-306-47529-4 0-7923-8452-0 ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2001 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at: http://kluweronline.com http://ebooks.kluweronline.com Dedication This book is dedicated to Christine and Valerie for all of the joy and happiness that they bring into my life This Page Intentionally Left Blank Preface This book is based on the earlier Kluwer title Circuit Design for CMOS/VLSI which was published in 1992 At that time, CMOS was just entering the mainstream as a technique for high-speed, high-density logic circuits Although the technology had been invented in the 1960’s, it was still necessary to include Section 1.1 entitled Why CMOS? to justify a book on the subject Since that time, CMOS has matured and taken its place as the primary technology for VLSI and ULSI digital circuits It therefore seemed appropriate to update the book and generate a second edition Background of the Book After loading the old files and studying the content of the earlier book, it became clear to me that the field is much more stable and well-defined than it was in the early 1990’s True, technological advances continue to make CMOS better and better, but the general foundations of modern digital circuit design have not changed much in the past few years New logic circuit techniques appearing in the literature are based on well-established ideas, indicating that CMOS has matured As a result of this observation, the great majority of the old files were abandoned and replaced with expanded discussions and new topics, and the book was reorganized to the form described below There are sections that didn’t change much For example, Chapter (which introduces MOSFETs) includes more derivations and pedagogical material, but the theme is about the same But, many items are significantly different For example, the earlier book contained about 60 pages on dynamic logic circuits The present volume has almost three times the number of pages dedicated to this important area In addition, the book has been written with more of a textbook flavor and includes problem sets Contents Chapter introduces the MOS system and uses the gradual-channel approximation to derive the square-law equations and basic FET models This sets the notation for the rest of the book Bulkcharge models are also discussed, and the last part of the chapter introduces topics from smalldevice theory, such as scaling and hot electrons viii Chapter is an overview of silicon fabrication and topics relevant to a CMOS process flow Basic ideas in lithography and pattern transfer are covered, as are items such as design rules, FET sizing, isolation, and latch-up This chapter can be skipped in a first reading, but it is important to understanding some problems that are specific to layout and fabrication issues It is not meant to replace a dedicated course in the subject Circuit design starts in Chapter 3, which is a detailed analysis of the static CMOS inverter The study is used to set the stage for all of the remaining chapters by defining important DC quantities, transient times, and introducing CMOS circuit analysis techniques Chapter concentrates on a detailed study of the electrical characteristics of FETs when used as voltage-controlled electronic switches In particular, the treatment is structured to emphasize the strong and weak points of nFETs and pFETs, and how both are used to create logic networks This feeds into Chapter 5, which is devoted entirely to static logic gates This includes fully complementary designs in addition to variants such as pseudo-nMOS circuits and novel XOR/XNOR networks Chapter on transmission gate logic completes this part of the book Dynamic circuit concepts are introduced in Chapter This chapter includes topics such as charge sharing and charge leakage in various types of CMOS circuit arrangements RC modelling is introduced, and the Elmore formulas for the time constant of an RC ladder is derived Clocks are introduced and used in various types of clocked static and dynamic circuits Dynamic logic families are presented in Chapter The discussion includes detailed treatments of precharge/evaluate ripple logic, domino logic cascades, self-resetting logic gates, single-phase circuits and others I have tried to present the material in an order that demonstrates how the techniques were developed to solve specific problems Chapter deals with differential dual-rail logic families such as CVSL and CPL with short overviews of related design styles The material in Chapter 10 is concerned with selected topics in chip design, such as interconnect modelling and delays, crosstalk, BSD-protected input circuits, and the effects of transmission lines on output drivers The level of the presentation in this chapter is reasonably high, but the topics are complex enough so that the discussions only graze the surface It would take another volume (at least) to justice to these problems As such, the chapter was included to serve as an introduction for other courses or readings Use as a Text There is more than enough material in the book for a 1-semester or 2-quarter sequence at the senior undergraduate or the first-year graduate level The text itself is structured around a first-year graduate course entitled Digital MOS Integrated Circuits that is taught at Georgia Tech every year The course culminates with each student completing an individual design project My objectives in developing the course material are two-fold First, I want the students to be able to read relevant articles in the IEEE Journal of Solid-State Circuits with a reasonable level of comprehension by the end of the course The second objective is more pragmatic I attempt to structure the content and depth of the presentation to the point where the students can answer all of the questions posed in their job interviews and plant visits, and secure positions as chip designers after graduation Moreover, I try to merge basics with current design techniques so that they can function in their positions with only a minimum amount of start-up time Problem sets have been provided at the end of every chapter (except Chapter 2) The questions are based on the material emphasized in the chapter, and most of them are calculational in nature Process parameters have been provided, but these can easily be replaced by different sets that might be of special interest Most of the problems have appeared on my homeworks or exams; others are questions that I wrote, but never got around to using for one reason or another I have tried to include a reasonable number of problems without getting excessive Students that can follow the level of detail used in the book should not have many problems applying the material SPICE simulations add a lot to understanding, and should be performed whenever possible 514 Now then, at the interface between the transmission line and the load, the voltage and the current must be continuous Mathematically, this means that For the incident wave, the voltage and current are related by If we try to match these values for the voltage and current to those of the load, we see that it cannot be done except in the special case where is true, i.e., a matched load This means that we must modify our initial guess for the line quantities and by noting that the wave equation has negatively travelling wave solutions and that we can use to construct the superposition as the total values Since these are defined on the line with impedance we can write and apply the load continuity conditions Physically, these equations tell us that when a wavefront hits an impedance discontinuity, a reflected wavefront will be generated and move back towards the source The amplitude of the reflected wave may be found by solving these equations for the reflection coefficient given by Transmission Lines This says that an incident wave voltage 515 will generate a reflected wave amplitude of where the value of (and hence, is determined by the value of the load impedance relative to Note that if then is a positive number, while gives a negative Only a matched load with eliminates reflections as indicated by To understand the consequences of the reflection coefficient, consider the terminated line shown in Figure 10.44 We will assume that the input voltage is as before This has the effect of launching a positively-travelling wave from the source to the load as described by The transit time from one end of the line to the other is given by so that a wavefront of amplitude reaches the load at Now, let us assume that the load simple resistor The load reflection coefficient is then given by such that the reflected wave has an amplitude of The load voltage at this time is given by KVL as is a 516 where we again note that can be positive or negative The reflected wave reaches the source at a time where it will be subject to reflection (back towards the load) From the drawing we see that the source impedance has been assume to be so the source reflection coefficient is This indicates a perfect reflection with inversion The reflected wave at the source is really the second wave travelling to towards the load, so we will call it It has a general value of The second positive wave reaches the load at a time second reflected wave has an amplitude of and is again subject to a reflection The The load voltage at this time is As time increases, the back-and-forth bouncing gives rise the infinite series which sums to in the limit where For our problem where we can substitute for and compute which reduces to as it should! This result becomes obvious when we note that the transmission acts like a simple Transmission Lines 517 wire after the transients decay away The main point to be remembered here is that it takes a finite amount of time for the transmission line effects to converge into the final value This consideration becomes very important at high frequencies Capacitive Load Now let us analyze the situation shown in Figure 10.45 where a transmission line with a length d is terminated with a load capacitor This problem is of interest because it models the situation where we are driving the input of a CMOS gate that is intrinsically capacitive We have chosen a source with an internal impedance of to get for simplicity The source voltage is once again chosen to be However, the presence of the source impedance changes the value that actually makes it to the transmission line At the input to the line given by we have so that represents the input impedance seen by the source circuitry (which is the series combination of the voltage source and The internal impedance and input impedance form a voltage divider with so that the launched pulse is given by as it propagates towards the capacitive load To analyze the effect of we want to compute the load reflection coefficient However, since the load is a pure capacitor, we will transform to s-domain where 518 and assume that the characteristics impedance is then given by is purely real The s-domain reflection coefficient such that where are the s-domain voltages To complete the analysis, we note that the launched pulse reaches the load capacitor after a transit delay The s-domain value is so that the reflected pulse is described by Rearranging and inverse transforming back to time-domain gives the reflected voltage as where is the time constant The total load voltage across the capacitor is calculated as which gives This is plotted in Figure 10.46 where we see that this is just the charging of the capacitor through the source impedance with a delay due to the transit time on the transmission line Since this is a highly idealized analysis with a matched source assumed, we must be careful about extending the behavior to a CMOS system However, it does illustrate the general problems involved Transmission Lines 519 MOSFET Driver Matching To apply our understanding of transmission line analysis to the problem of CMOS drivers, consider the situation illustrated in Figure 10.47(a) where a logic gate is connected to a transmission line At the FET level [Figure 10.47(b)], we are concerned with trying to drive the line impedance with the transistor circuitry Since is a real number, we might be tempted to use the linearized FET resistances 520 to choose the device aspect ratios and that would match the line impedance The problem with this approach, of course, is that and are defined as linear resistances, while the MOSFETs are intrinsically nonlinear devices Because of this problem, some designs insert a resistance R in between the driver and the line to swamp out some of the nonlinear variations This is illustrated in Figure 10.48 The actual value of R depends upon the effect of the FETs, but since these will generally be quite large (to handle the large capacitance), as shown is a reasonable first estimate Damped Driver One problem with driving an open line is that noise problems can destroy the integrity of the data transmission Because of this problem, terminated bus designs like those used in high-speed bipolar ECL systems have been proposed for multi-signal CMOS transceiver arrangements The main idea is shown in Figure 10.49; resistors are added to the ends of the lines to prevent reflections; is the terminator supply voltage Each unit can act as a transmitter (X-section) or as a receiver (R-section), with arbitration performed by the system controller The resistors provide pull-up action to for a high voltage, while the line voltage is pulled down by a transmitter circuit toward ground if a low voltage is to be placed on the line This is quite different from the situations discussed above where the chip power supply was responsible for driving the line high When a transmitter sends a signal to the bus, the line will react with and some reflections may occur One way to overcome this is using the circuit shown in Figure 10.50 which is used to drive the line and provide damping.8 To understand the operation of the circuit, suppose that initially we have With this applied, Mn1 and Mn2 are in cutoff, while Mp, Mn3 and Mn4 are ON This gives an output voltage of When is switch to a high voltage the output from the inverter made up of Mp1 and Mn1 goes low Note that the series combination of Mn2 and Mn3 connect the gate and drain of Mn4 The inverter chain is used to delay the turnoff of Mn3 If we design Mn1 to have a small aspect ratio, then Mn4 will continue to conduct for a short time after the input transition This provides damping to ground that is eventually turned off when Mn3 goes into cutoff Once Mn4 is off, the output is pulled to the terminator voltage Problems such as these tend to be more critical as the bus speeds and number of connected units increase It is clear that much research will be devoted towards the problems in the future This design technique has been termed GTL by its developers for “Gunning Transistor Logic” Problems 521 10.4 Problems [10-1] Consider a simple doped poly interconnect line that is wide and has a sheet resistance of 25 A FET is made with an aspect ratio of (W/L)=4 such that the process variables are and (a) Find the length of the line where the line resistance is equal to one-half of the LTI nFET resistance (b) Suppose that we coat the poly with W which produces a silicide that has a sheet resistance of What is the length of the line in this new material that gives one-half of [10-2] The interconnect line described in Problem [10-1] has a thickness of and is routed over an isolation oxide that has a thickness of (a) Find the capacitance for the line using the ideal parallel-plate formula (b) Find the line capacitance accounting for contributions from fringing fields (c) What is the percentage error in the total line capacitance if fringing fields are ignored? 522 [10-3] Consider a layer of doped polysilicon that has a resistivity of (a) Calculate the sheet resistance if the layer is 6000Å thick (b) The thickness of the layer is chosen to be 5500Å The lithographic resolution of the process sets the minimum width at 0.4 microns Find the length d (in microns) for an interconnect that has a line resistance of [10-4] An interconnect line is described by the cross-sectional view shown in Figure 10.3(a) with dimensions of and Silicon dioxide is used as the insulator The line has a length of 35 and a sheet resistance of 0.05 (a) Find by including fringing fields as in equation (10.10) (b) Find the line resistance (c) Construct RC ladder equivalent networks for m = and m = Then find the time constant fo each (d) Assume that the m = model is more accurate, find the percentage error if the m = result is used instead [10-5] An interconnect line has a sheet resistance of length of The line has a width of 0.8 given in equation (10.45) are used with volts and ohms and a line capacitance per unit The results of the distributed analysis volts as our reference We know that (a) Find the equation for the interconnect-induced time delay as a function of the line length d (b) Plot the delay for distances up to 50 [10-6] Prove explicitly that any function is a solution to the wave equation, i.e., that Hint: First define the composite variable and then calculate the the chain rule For example, the start the time derivative calculation with and derivatives using and then use this to compute the second derivative [10-7] Show explicitly that the function with A = constant satisfies the wave equation [10-8] Two coupled interconnect lines are described by the cross-sectional view shown in Figure 10.17 with dimensions of h = 0.6 and w = 0.4 Silicon dioxide is used as the insulator The line has a length of 65 (a) Calculate the coupling capacitance if S = w (b) Calculate the coupling capacitance if the spacing is increased to S = 3w [10-9] Calculate the phase velocity of a line that uses silicon dioxide as an insulator [10-10] Silicon nitride has a relative permittivity of about What is the phase velocity of a signal if nitride is used as the dielectric? References 523 [10-11] An oxy-nitride (silicon dioxide-silicon nitride combination) has a relative permittivity of (a) Calculate the phase velocity of a line that uses this material as an insulator (b) Find the signal delay in units of [10-12] Consider the oxy-nitride line describe [10-13] Consider the parallel RC transmission line termination shown in Figure P10.1 A shunt resistor is sometimes used in this manner to help match the load to the transmission line Find the sdomain reflection coefficient for this case 10.5 References The books below provide detailed discussions on the topics presented in this chapter [1] H B Bakoglu, Circuits, Interconnection and Packaging for VLSI, Addison-Wesley, Reading, MA, 1990 [2] A K Goel, High-Speed VLSI Interconnections, John Wiley & Sons, New York, 1994 [3] B Gunning, L Yuan, T Nguyen, and T Wong, “A CMOS Low-Voltage-Swing TransmissionLine Transceiver,” ISSCC92 Technical Digest, pp.58-59, 1992 [4] E G Friedman (ed.), Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press, New York, 1995 [5] C R Paul, Multiconductor Transmission Lines, John Wiley & Sons, New York, 1994 [6] R K Poon, Computer Circuits Electrical Design, Prentice-Hall, Englewood Cliffs, NJ, 1994 [7] M Shoji, High-Speed Digital Circuits, Addison-Wesley, Reading, MA, 1996 [8] S Ramo, T Van Duzer, and J Whinnery, Fields and Waves in Communication Electronics, 3rd ed., John Wiley & Sons, New York, 1994 This Page Intentionally Left Blank Index A active area (on chip) adder, AOI adder, TG AOI logic aspect ratio (W/L ) 74 230 276 193 13 B backward propagating logic BiCMOS bipolar junction transistor bird’s beak (in LOCOS) bit line DRAM SRAM body bias bootstrapping breakover voltage bulk charge QB bulk mobility bulk terminal 308 506 95, 506 76 311 234 319 96 29 charge keeper circuits 379 charge leakage 287 charge pump 319 charge sharing 303 CLA (Carry Look-Ahead) adder 396 clocked CMOS 331 clock distribution 490 clock generation 335 clock signal 321 clock skew 490 CMP 77 coefficients of capacitance 497 complementary error function 486 complementary FET pair 103 complex logic gates 193, 215 composite insulators (DRAM) 315 contact resistance 92 coupling capacitance 493 CPL (Complementary Pass-transistor Logic) 454 critical voltages (VTC) 105 current source (in CMOS) 472 crosstalk 492 C Cascode-voltage switch logic (CVSL) 437 capacitance, FET MOS gate 25 drain/source 34 capacitance output 113 line (interconnect) 479 channel voltage 11 channel length L channel-length modulation 15 characteristic impedance 512 D DCVSPG DRAM depletion capacitance (FET) depletion charge (MOS) defect density design rules device transconductance nFET pFET differential amplifier 466 311 28 99 90 13 20 469 526 differential current-switch logic diffusion equation diode input protection domino logic DPL (dual-transistor pass logic) drain, nFET drain-source resistance drawn channel length driver chains dual-rail logic D-type flip-flop (DFF) latch dynamic nMOS logic dynamic pMOS logic dynamic CVSL dynamic logic gate 453 485 499 369 463 23 72 144 435 278 233 350 363 447 287, 349 E ECDL effective channel length electron temperature electrostatic discharge (ESD) Elmore formula encroachment (in LOCOS) etching error function evaluation (dynamic logic) exclusive-OR (XOR) exclusive-NOR (XNOR) 451 72 52 498 174 76 69 486 351 224 224 F Fermi potential nFET pFET field-effect field implant field oxide (FOX) field regions (of chip) fixed charge (oxide) flatband voltage frequency, clock fringing capacitance 21 76 76 74 321 477 G gate capacitance gate, MOSFET gate overlap gate overhang 25 72 92 gate oxide gate oxide short gate-drain capacitance gate-source capacitance generation current (pn junction) gradual-channel approximation guard rings Gunning Transistor Logic (GTL) 100 27 27 36 11 99 520 H hot electrons high-to-low time H-trees 52 115 491 I input high voltage input low voltage input protection circuits interconnects (on-chip) inversion layer inverter, static CMOS ion implantation ion implantation, threshold adjust 107 107 498 477 103 64 J junction capacitance junction leakage 27 289 L layout editor latch latch-up lateral diffusion LDD MOSFET line capacitance line resistance lithography LOCOS logic trees (CVSL) low-to-high time 85 233 94 72 58, 72 479 478 68 74 441 117 M matched termination mask master-slave flip-flop midpoint voltage mirror circuits MOS structure 514 68 279 108 226 527 MOSFET MOSFET chains sizing transient response multiplexors nFET pFET split-array TG MODL (multiple-output domino logic) multiplier, serial NORA 381 173 186 187 188 272 392 415 N NAND (static CMOS) narrow-width effects nFET nitrides nMOS-nMOS dynamic cascades nMOS-pMOS dynamic cascades noise margins nonlinear mobility NOR (static CMOS) NORA (No Race) Logic n-well 19, 195 48 75 359 367 109 52 206 408 73, 59 OAI logic ON (oxy-nitride) layers OR gate output capacitance output high voltage output low voltage overlap capacitance overhang (gate) oxide capacitance oxide trapped charge 193 316 273 113 104 104 26 92 4, 74 P parity Pearson distributions perimeter length (sidewall) phase velocity photolithography photoresist physical design polysilicon positive logic power dissipation (inverter) 155 66 31 511 68 68 85 7, 63 105 140 pn junction process transconductance (k’) nFET pFET precharge/evaluate logic projected range (ion implant) pseudo-nMOS p-well process 35 13 22 350 65 245 84 R rapid thermal anneal RAM (random-access memory) SRAM DRAM RC ladder analysis RC model FET inverter reactive ion etching (RIE) recessed oxide (ROX) reflection coefficient refresh operation (DRAM) register, TG registration marks resist reticle (mask) ripple-carry adder 65 234 311 173 22 120 69 76 515 318 276 86 68 68 397 S sample-set differential logic (SSDL) 449 saturation (in a FET) 14 saturation velocity 54 saturation voltage 14 scaling theory, general 37 Schmitt trigger 238 self-aligned MOSFET 71 Self-resetting logic 404 sense amplifier 313 series FET chains 167 sheet resistance 476 shift register 328 short-channel effects 45 sidewall capacitance 30 signal races 408 silicides 83 silicon controlled rectifier 94 silicon dioxide 62 silicon nitride 75 single-phase logic 416 square-law equations 528 nFET pFET SRAM SR latch stacked capacitors (DRAM) static logic gate static RAM stepper step input waveform straggle stress-relief oxide substrate subthreshold leakage subthreshold slope surface charge surface mobility surface potential surround design rule switching frequency (gate) symmetric design (inverter) 14 22 234 232 318 193 234 68 124 65 75 295 295 29 91 118 134 T thermal oxide threshold voltage gain (through a pFET) inverter loss (through an nFET) nFET pFET thick-oxide MOSFETs transconductance nFET pFET transfer curve nFET bipolar transistor transmission gate definition transmission line analysis trench capacitor (DRAM) trench isolation tri-state circuits general output drivers TSPC (True single-phase clock) logic 62 164 108 157 21 502 13 22 17 506 259 510 317 78 243 505 419 U unity gain line 108 V vias voltage transfer curve (VTC) 86 105, 222 W wave equation word line DRAM SRAM 511 311 235 X XOR/XNOR 224, 251, 274 Y yield, IC fabrication 99 Z Zener knee 499 ... CMOS LOGIC CIRCUIT DESIGN This Page Intentionally Left Blank CMOS LOGIC CIRCUIT DESIGN John P Uyemura Georgia Institute of Technology KLUWER... earlier Kluwer title Circuit Design for CMOS/ VLSI which was published in 1992 At that time, CMOS was just entering the mainstream as a technique for high-speed, high-density logic circuits Although... True, technological advances continue to make CMOS better and better, but the general foundations of modern digital circuit design have not changed much in the past few years New logic circuit techniques
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