FDA2100LV x 180 W / x 300 W PWM digital input power amplifier with built-in diagnostics features and step-up driver Datasheet - production data Description *$*36 TQFP64 (exposed pad up) Features  Integrated 105 dB D/A conversion  I2S & TDM digital input (3.3/1.8 V)  Input sampling frequency: 44.1kHz, 48 kHz, 96 kHz, 192 kHz  Step-up driver included  EMI control for FM/AM compatibility  Dithering possibility  Capable to operate down to V (e.g."start-stop")  V - 35 V operating range (RL = Ω)  Low component count output lowpass filter  Output low-pass filter included in the feedback  Low radiation function (LRF)  High output power capability – x 80 W/4 Ω @ 25 V, kHz, 10 % THD – x 120 W/4 Ω @ 30 V, kHz, 10 % THD – x 150 W/2 Ω @ 25 V, kHz, 10 % THD  Full I2C bus driving (3.3/1.8 V): – I2C bus digital diagnostics (including DC and AC load detection); AC and DC loudspeaker diagnostic  Very flexible fault detection though integrated diagnostic  Protected against several kinds of misconnections The FDA2100LV is a new BCD technology dual bridge class D amplifier, specially intended for car radio applications Thanks to the BCD6-SOI (Silicon On Insulation) technology it is possible to integrate a high performance D/A converter together with powerful MOSFET output amplifier working in class D, to get an outstanding efficiency with respect to the standard class AB The D/A conversion on board allows the performance to reach an outstanding 110 dB S/N ratio with 105 dB of dynamic range The feedback loop includes the output L-C low-pass filter, allowing superior frequency response linearity and lower distortion independently of the inductor and capacitor quality A full diagnostics array communicates the status of each speaker through the I2C bus The possibility to control the device by means of the I2C bus makes FDA2100LV very flexible Thanks to the solutions implemented to solve the EMI problems, the device can intended to be used in the standard single DIN car-radio box together with the tuner A built-in step-up driver allows up to 150 W output power with the standard 14 V supply voltage The FDA2100LV is moreover compliant to the most recent OEM specifications for low voltage operation (so called 'start-stop' battery profile during engine stop), helping car manufacturers to reduce the overall emissions and thus contributing to environment protection  Offset detector (play or mute mode) Table Device summary  Two independent short circuit protections  Clipping detector Order code  C-MOS compatible enable pin (3.3/5 V) FDA2100LV  ESD protection FDA2100LV-T  Package: TQFP64 exposed pad up September 2013 This is information on a product in full production Rev Package TQFP64 (e.p.u.) Packing Tray Tape & reel 1/61 www.st.com Contents FDA2100LV Contents Block diagram and pins description Electrical specifications 10 2.1 Absolute maximum ratings 10 2.2 Thermal data 10 2.3 Electrical characteristics 10 General introduction 18 3.1 New feedback topology 18 3.2 LC filter design 18 3.3 Load possibilities 19 Operation mode 20 4.1 Standby mode 20 4.2 Legacy mode 20 4.3 I2C mode 20 4.4 I2C functions 21 4.5 AM operation mode 22 4.6 EMI and dithering 23 Mute function 24 Diagnostics functional description 25 6.1 2/61 Load detection 25 6.1.1 Turn-on diagnostic 26 6.1.2 AC/DC load diagnostic 27 6.1.3 Permanent diagnostic 34 6.1.4 Output current digital acquisition 34 6.2 ExtTherm pin function 37 6.3 Special cases: behavior under mis-connection conditions 38 6.3.1 Case 38 6.3.2 Case 38 6.3.3 Case 38 Rev FDA2100LV Contents 6.4 Over-current limit threshold selection Isc 39 6.5 Suggested diagnosic procedure 39 Integrated step-up 40 7.1 Functional description 40 7.2 Step-up settings 40 7.3 Turn-on procedure 40 Application schematics 41 Low voltage (“start stop”) operation 42 10 I2S bus interface 43 11 I2C bus interface 46 12 11.1 Writing procedure 47 11.2 Reading procedure 47 11.3 Data validity 48 11.4 Start and stop conditions 48 11.5 Byte format 48 11.6 Acknowledge 48 11.7 I2S and I2C relationship 49 I2C register 50 12.1 IB0-ADDR:”00000” 50 12.2 IB1-ADDR:”00001” 50 12.3 IB2-ADDR:”00010” 51 12.4 IB3-ADDR:”00011” 52 12.5 IB4-ADDR:”00100” 52 12.6 IB5-ADDR:”00101” 53 12.7 IB6-ADDR:”00110” 53 12.8 IB7-ADDR:”00111” 54 12.9 IB8-ADDR:”10000” 54 12.10 IB9-ADDR:”10001” 55 12.11 IB10-ADDR:”10010” 55 Rev 3/61 Contents FDA2100LV 12.12 DB1-ADDR:”10000” 56 12.13 DB2-ADDR:”10001” 56 12.14 DB3-ADDR:”10010” 57 12.15 DB4-ADDR:”10011” 57 12.16 DB5-ADDR:”10100” 58 12.17 DB6-ADDR:”10101” 58 13 Package information 59 14 Revision history 60 4/61 Rev FDA2100LV List of tables List of tables Table Table Table Table Table Table Table Table Table Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Device summary Pins list description Absolute maximum ratings 10 Thermal data 10 General and audio characteristics 10 Diagnostics 13 Step-up 17 Interfaces 17 Operation mode 20 DC test diagnostic available settings and relative thresholds and signal amplitudes 27 AC test diagnostic available settings and relative thresholds and signal amplitudes 28 Step up settings 40 IB0-ADDR:”00000” 50 IB1-ADDR:”00001” 50 IB2-ADDR:”00010” 51 IB3-ADDR:”00011” 52 IB4-ADDR:”00100” 52 IB5-ADDR:”00101” 53 IB6-ADDR:”00110” 53 IB7-ADDR:”00111” 54 IB8-ADDR:”10000” 54 IB9-ADDR:”10001” 55 IB10-ADDR:”10010 55 DB1-ADDR:”10000” 56 DB2-ADDR:”10001” 56 DB3-ADDR:”10010” 57 DB4-ADDR:”10011” 57 DB5-ADDR:”10100” 58 DB6-ADDR:”10101” 58 Document revision history 60 Rev 5/61 List of figures FDA2100LV List of figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 6/61 Block diagram Pins connection diagram (top view) Switching frequency scheme 22 Minimum duty cycle for the PWM output square wave diagram 22 Hardware mute application schematic 24 Load diagnostic diagram 26 Examples of 'soft-short conditions' allowed 27 AC load diagnostic result representation considering the impedance Z in the complex plane (Lfilter = 22µH) 30 AC load diagnostic result representation considering the impedance Z in the complex plane (Lfilter = 10µH) 31 Impedance phase and magnitude frequency plots of a ways speaker system 32 AC load diagnostic example in practice 32 Permanent diagnostic 34 Current sensing mode 1, ADC typical characteristic 35 Current sensing mode 2, ADC typical characteristic 36 External temperature warning application schematic 37 Flow chart of diagnostic procedure 39 Application schematic with step-up 41 Application schematic without step-up 41 Worst case battery cranking curve sample 42 Worst case battery cranking curve sample 42 I2S standard data format 43 TDM4 data format 44 TDM8 data format 44 I2S interface 45 I2C bus protocol description 46 Reading procedure 47 Without/with auto-increment reading procedure 48 FDA2100LV communication bus interaction scheme 49 I2C programming possibilities 49 TQFP64 (exposed pad up) mechanical data and package dimensions 59 Rev FDA2100LV Block diagram and pins description Figure Block diagram )  $IG 0  $ 'ND ) $IG  $ 6DD #OMP  362   ! 6DD 6BAT  !N 0   !N 'ATE DRIVER ! 'ND   )SET0ROT 35 'ND  -UTE   %XT4HER 4ES T # #LOCK   $$)!' )3 DATA  # $ATA  %NABLE )3 3INC %NABLE   0,,  )3 #LOCK %NABLE 0,,?&ILTER         )# #URRENT 'ENERATORS !RRAY 3CRAMBLER )3 INTERFACE 074R ANSRESISTANCE 0OWERAMPLIFIER  &EEDBACK  /UT  /UT  /UT  /UT  &EEDBACK  &EEDBACK  /UT  /UT  /UT  /UT  &EEDBACK )NTERPOLATION  OISE3HAPING #URRENT 'ENERATORS !RRAY 3CRAMBLER 3TEP UP DRIVER 074R ANSRESISTANCE 0OWERAMPLIFIER   'ND 6DD 6DD   'ND  'ND  'ND  6DD 4! "  6DD  *$3*36 # 'ND .# # # # # # # # # # # # 'ND 4!" Figure Pins connection diagram (top view)                 &EEDBACK   &EEDBACK /UT   /UT /UT   /UT 6DD   6DD 6DD   6DD /UT   /UT /UT   /UT &EEDBACK   &EEDBACK 'ND   'ND #   35 'ND )3 #LOCK   'ATE DRIVER )3 3INC   6BAT )3 $ATA   #OMP 4EST   ) )# #LOCK   ) )# $ATA   %NABLE ! 6DD $ 6DD ! 'ND !N 0 !N 362 )SET0ROT %XT4HER $IG $IG 0 $ 'ND -UTE 0,,?&ILTER %NABLE %NABLE                 #$$)!' Block diagram and pins description *$3*36 Rev 7/61 60 Block diagram and pins description FDA2100LV Table Pins list description Pin # Pin name 64 N.C 63 Gnd1- 51-62 N.C 50 Gnd2- 49 TAB 48 Feedback2- 47 Out2- Channel half bridge output - 46 Out2- Channel half bridge output - 45 Vdd2- Channel half bridge power supply - 44 Vdd2+ Channel half bridge power supply + 43 Out2+ Channel half bridge output + 42 Out2+ Channel half bridge output + 41 Feedback2+ 40 Gnd2+ 39 N.C 38 I2S-Clock I2S/TDM clock Input 37 I2S-Sinc I2S/TDM sinc Input 36 I2S-Data I2S/TDM data Input 35 Test Test pin (do not use) 34 I2C-Clock I2C data Clock 33 I2C-Data I2C data input 32 CD/DIAG Clip detector and diagnostic output: over-current protection, thermal warning, offset detection 31 Enable Chip enable 30 Enable Chip enable 29 PLL_Filter PLL filter network 28 Mute 27 D-Gnd Digital ground 26 Dig-P Positive digital supply V(svr)+1.65 (internally generated) 25 Dig-N Negative digital supply V(svr)-1.65 (internally generated) 24 ExtTher External thermal protection input 23 IsetProt Current protection resistor setting 22 SVR Supply voltage ripple rejection capacitor 21 An-N Negative analog supply V(svr)-1.65 (internally generated) 20 An-P Positive analog supply V(svr)+1.65 (internally generated) 8/61 Function Not connected Channel 1, half bridge power ground Not connected Channel 2, half bridge power ground TAB connection Channel half bridge feedback - Channel half bridge feedback + Channel 2, half bridge power ground + Not connected Mute input (6 µA source current) Rev FDA2100LV Block diagram and pins description Table Pins list description (continued) Pin # Pin name Function 19 A-Gnd Analog ground 18 D-Vdd Digital power supply 17 A-Vdd Analog power supply 16 Enable 15 I2 Step-up current limiting reference 14 I1 Step-up current limiting input 13 Comp Step-up compensation input 12 Vbat 11 Gate-driver 10 SU-Gnd Step-up power ground Gnd1+ Channel 1, half bridge power ground + Feedback1+ Out1+ Channel half bridge output + Out1+ Channel half bridge output + Vdd1+ Channel half bridge power supply + Vdd1- Channel half bridge power supply - Out1- Channel half bridge output - Out1- Channel half bridge output - Feedback1- Chip enable Power supply (battery) External PowerMOS gate drive output Channel half bridge feedback + Channel half bridge feedback - Rev 9/61 60 Electrical specifications FDA2100LV Electrical specifications 2.1 Absolute maximum ratings Table Absolute maximum ratings Symbol Vop Vpeak Parameter Test conditions Operating supply voltage Peak supply voltage Value Unit RL = Ω 30 V RL = Ω 35 V t = 50 ms Max 50 V Vi2c I C bus pins voltage - -0.3 to 4.6 V Vi2s I2S bus pins voltage - -0.3 to 4.6 V Enable 1,2 Enable pins voltage - -0.3 to V CD/DIAG CD/DIAG pin - -0.3 to V 30V Max 7.2 A 35V Max A - 200 kHz - 55 to 150 °C - –40 to 105 °C IO Fs max Tstg, Tj Tamb Output peak current (repetitive f > 10 Hz)(1) Max input sample rate Storage and junction temperature(2) Operative temperature range For internal current limitation value refer to Section 6.4 A suitable heatsink should be used to keep Tj inside specified limits 2.2 Thermal data Table Thermal data Symbol Rth j-case 2.3 Parameter Thermal resistance junction-to-case Max Value Unit °C Electrical characteristics Refer to the test circuit, Vdd = Vbatt = 14.4 V; RL = Ω; f = kHz; Tamb = 25 °C; unless otherwise specified Tested at Tamb = 25 °C and Thot = 105 °C; functionality guaranteed for Tj = -40 °C to 150 °C Fsample = 48 kHz; PWM 'in phase'; unless otherwise specified Table General and audio characteristics Symbol Parameter Test condition RL = Ω Vdd, Vbatt Supply voltage range RL = Ω Typ Max Unit - 18(1) V - (1) 30 V - 35(1) V RL = Ω 10/61 Min Rev Diagnostics functional description FDA2100LV 6.3 Special cases: behavior under mis-connection conditions 6.3.1 Case In this case, the device has an anomalous resistive path (Rsc) to ground or to the positive supply present on one "half bridge" output of the channel N before turn-on (with N = or 2) If I(Rsc) > 30 mA, the channel N is maintained in 3-state mode because it is considered in unsafe condition (short or resistive path to ground or ti +Vs) If I(Rsc) become < mA the channel N is considered in safe condition (no short or resistive path to ground or to +VS), then, after ~200 ms, starts to work in mute condition The unmute soft transition is automatically generated 6.3.2 Case In this case, the device has an anomalous resistive path (Rsc) to ground or to the positive supply present on one "half bridge" output of the channel N after turn-on If Iout > Isc, the channel N is kept in 3-state mode Note: Isc is defined by the resistor connected between the pin 36 (IsetProt) to ground according to Section 6.4 With the channel N in 3-state mode: a) if I(Rsc) > 30 mA, the channel N is maintained in 3-state mode because it is considered in unsafe condition (short or resistive path to ground or ti +Vs) b) If I(Rsc) become < mA the channel N is considered in safe condition (no short or resistive path to ground or to +VS), then, after ~200 ms, starts to work in mute condition The unmute soft transition is automatically generated The over-current event is stored in the I2C Data byte 6.3.3 Case In this case, the device has an anomalous resistive path across the outputs of the bridge N If Iout > Isc, the channel N is kept in 3-state mode After ~200 ms, starts to work in mute condition The unmute soft transition is automatically generated The over-current event is stored in the I2C Data byte Because the device is self-protected, it is not mandatory to reduce the input signal in case of over-current protection intervention 38/61 Rev FDA2100LV 6.4 Diagnostics functional description Over-current limit threshold selection Isc The output power bridge current threshold at which the protection circuit is activated (Case and Case 3) depends on the value of the external resistor placed between the pin 23 (IsetProt) to ground according to the following expression: Isc = 10 x 2200/R8 A The default and minimum value of R8 to be used depend on Vdd power supply voltage:  for Vdd = 6-30 V: 2.2 kΩ, 1% tolerance that gives Isc = 10 A  for Vdd = 30-35 V: 3.6 kΩ, 1% tolerance that gives Isc = 6.1 A The maximum allowable value of this resistor is 10 kΩ (Isc = 2.2 A) 6.5 Suggested diagnosic procedure In the following diagram it is described the procedure to follow to guarantee a proper use of diagnostic feature Figure 16 Flow chart of diagnostic procedure (QDEOHIURPWR,&PRGH ,&ZULWH 3:021FKDQGFK  'LDJQ'&ORDGWHVW(1$%/('   ,&UHDG'%  ,& DFFHVVLEOH"  '%,%5: 2."  V(Ilim), a current limiting is activated Thanks to the low-pass filter R5 and C5, the current limiting works on the average value A current limiting activation flag is available on the I2C bus DB1 - D7 7.2 Step-up settings Through I2C bus, it is possible to select the following different step-up settings:  Step-up enable/disable  Output voltage selection (18 V, 20 V, 22.5 V, 25 V)  Step-up always on or turned off @ Tchip > 150 °C and on again @ Tchip < 135 °C  Step-up soft start selection time (2 ms, ms, 10 ms)  Higher time is recommended because reduces the turn-on peak current  Step-up clock dithering (on/off) Dithering spreads the harmonics produced by the step-up square wave, reducing the peak amplitude (5 -10 dB)  Maximum ton of the external PowerMOS selection This function is needed to avoid a too large current flowing in the PowerMOS in case of low battery voltage In case of low battery voltage the step-up output voltage is no more regulated by the feedback but depends only by the input voltage and the duty cycle D = ton/(ton + toff) of the external PowerMOS In the following table ton versus the I2C selection at different I2S sync clock is shown Table 12 Step up settings 7.3 IB4 – D0, D1 Fclock 35 kHz - 50 kHz Fclock = 96 kHz and 192 kHz 00 – Min 0.0586 / fclock 1.22 µs 01 – Med 0.0664 / fclock 1.38 µs 10-11 - Max 0.0742 / fclock 1.55 µs Turn-on procedure The step-up must be enabled through I2C bus together with or after the PWM power amplifiers It is not allowed to enable the step-up before the PWM power amplifiers 40/61 Rev FDA2100LV Application schematics Application schematics Figure 17 Application schematic with step-up      #           /UT /UT /UT   &$!,6  /UT     )3 #LOCK   )3 3INC   )3 $ATA   )3 #LOCK  )3 $ATA  6S                    6DD #$$)!' %NABLE %NABLE %NABLE GND 6DD -UTE *$3*36 Figure 18 Application schematic without step-up      #             /UT /UT /UT &$!,6    )3 #LOCK  )3 3INC  )3 $ATA  )3 #LOCK  )3 $ATA  /UT    6S   6DD                  #$$)!' %NABLE %NABLE %NABLE 6DD GND -UTE *$3*36 Rev 41/61 60 Low voltage (“start stop”) operation FDA2100LV Low voltage (“start stop”) operation The most recent OEM specification are require automatic stop of a car engine at traffic light, in order to reduce emissions of polluting substances Thanks to its innovating design, the FDA2100LV allows a continuous operation when battery falls down to 6/7V during such conditions, without producing pop noise The maximum system power will be reduced accordingly Worst case battery cranking curves are shown below, indicating the shape and duration of allowed battery transitions Figure 19 Worst case battery cranking curve sample 6BATT6 6 6 6 6 T T T T T T T TS '!0'03 V1 = 12 V; V2 = V; V3 = V; V4 = V t1 = ms; t2 = 50 ms; t3 = ms; t4 = 300 ms; t5 =10 ms; t6 = s; t7 = ms Figure 20 Worst case battery cranking curve sample 6BATT6 6 6 6 T T T T V1 = 12 V; V2 = V; V3 = V t1 = ms; t2 = ms; t3 = 15 ms; t5 = s; t6 = 50 ms 42/61 Rev T TS '!0'03 I2S bus interface FDA2100LV 10 I2S bus interface The FDA2100 accepts the I2S standard format that could be Time Division Multiplexed (TDM) I2S bus is made up of three lines: the clock lines (SCK), the sync line (WS) and serial data line (SD) where 32 bits words are sent Note that only the first 20 bits received per word are processed and that WS frequency has to be always the same as audio sampling frequency ƒs According to I2C settings, audio signals can be sent with the following data format:  I2S standard  TDM channels mode  TDM channels mode  TDM channels mode  TDM channels mode  TDM channels mode  TDM channels mode Figure 21 I2S standard data format FS XFS 3#+ 73 #(-3"FIRST #(-3"FIRST 3$ '!0'03 Rev 43/61 60 I2S bus interface FDA2100LV TDM channels  devices, channels driven with data lines  bits to properly receive data: –  IB1[5-4] bits to recognize TDM4 channels and TDM4 modes or For each channel, the serial data is transmitted with the MSB first Figure 22 TDM4 data format TH MAX TH MIN 43#+ 3#+ 73 3$ )"; = #H-3" FIRST #H-3"IRST F 8 #H-3"FIRST #H-3"FIRST 3$ )"; = '!0'03 TDM channels  devices, channels driven with data lines  bits to properly receive data:  – IB1[5-4] bits to recognize TDM8 channels – IB4[7-6] bits to select TDM8 mode for channel selection For each channel, the serial data is transmitted with the MSB first Figure 23 TDM8 data format TH MAX H TH MIN 43#+ 3#+ 73 #H #H 8 8 8 3$ 8 #H #H 8 8 3$ 8 8 #H #H 8 8 8 8 #H #H )"; = )"; = 3$ )"; = 3$ )"; = '!0'03 44/61 Rev I2S bus interface FDA2100LV I2S Standard format Refer to I2S bus specification for details and timing TDM format  WS changes on falling edge of SCK, one clock period before the MSB is transmitted  WS does not need to be symmetrical, duration is two period of SCK, max duration is as here specified:  – th,max = 127 TSCK in TDM channels – th,max = 255 TSCK in TDM channels For other timing, refer to I2S bus specification I2S Interface configuration: IB1[5-4], IB4[7-6] IB1[5-4] IB4[7-6] 00 xx I2S standard 01 xx TDM 4ch mode 10 xx TDM 4ch mode 11 00 TDM 8ch mode 11 01 TDM 8ch mode 11 10 TDM 8ch mode 11 11 TDM 8ch mode Figure 24 I2S interface &$! 3#+ 0AD )NPUT #ELL )NPUT#ELL 73 0AD )NPUT#ELL 3$ 0AD )NPUT#ELL #ORE '!0'03 Rev 45/61 60 I2C bus interface 11 FDA2100LV I2C bus interface Data transmission from microprocessor to the FDA2100LV and viceversa takes place through the wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected) When I2Cbus is active any operating mode of the IC may be modified and the diagnostic may be controlled and results read back The protocol used for the bus is depicted in Figure 25 and comprises:  a start condition (S)  a chip address byte (the LSB bit determines read/write transmission)  a subaddress byte  a sequence of data (N-bytes + acknowledge)  a stop condition (P) Figure 25 I2C bus protocol description 3 !DDRESS ! 3UBADDRESS ! $ATA  0   !DDRESS       27 3UBADDRS  8 8 ) 35"! 35"! 35"! 35"! 35"! $ATA  $!4! $!4! $!4! $!4! $!4! $!4! $!4! $!4! '!0'03 I2 C The address are: Address = 1101000 Address = 1101001 Address = 1101010 Address = 1101011 Description: 46/61 – S = Start – R/W = '0' => Receive-Mode (Chip could be programmed by uP) – I = Auto increment; when 1, the address is automatically incremented for each byte transferred – X: not used – A = Acknowledge – P = Stop – MAX CLOCK SPEED 400kbit/sec Rev ... tested at ATE) Tested in 00 configuration only Not tested at ATE 12/61 Rev FDA2100LV Electrical specifications Table Diagnostics Symbol Parameter Test condition Min Typ Max Unit Turn on test... the device with dedicated I2C setup: Fast startup mode IB7 [D4-D0] = 00110 In this case diagnostic is working, but less reliable and pop-generating After fast startup, it is strongly suggested... from I2S are ignored until time T6 Un-muting starts after T6 If DC diagnostic is not selected, un-muting starts after T2 Startup and diagnostic timing can be squeezed by a factor around /50 starting-up