tài liệu lập trình PLC S7 300

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tài liệu lập trình   PLC S7 300

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S7-300 Instruction List CPU 312 IFM, 314 IFM, 313, 314, 315, 315-2 DP, 316-2 DP, 318-2 6ES7 398-8AA03-8BN0 Edition Contents Contents Contents Address Identifiers and Parameter Ranges Abbreviations and Mnemonics 12 Registers 14 Examples of Addressing 16 Execution Times with Indirect Addressing 20 List of Instructions Bit Logic Instructions Bit Logic Instructions with Parenthetical Expressions ORing of AND Operations Logic Instructions with Timers and Counters Word Logic Instructions with the Contents of Accumulator Evaluating Conditions Using AND, OR and EXCLUSIVE OR Edge-Triggered Instructions Setting/Resetting Bit Addresses Instructions Directly Affecting the RLO Timer Instructions Counter Instructions Load Instructions Load Instructions for Timers and Counters Transfer Instructions Load and Transfer Instructions for Address Registers Load and Transfer Instructions for the Status Word Load Instructions for DB Number and DB Length Integer Math (16 Bits) Integer Math (32 Bits) Floating-Point Math (32 Bits) Square Root and Square Instructions (32 Bits) Logarithmic Function (32 Bits) Trigonometrical Functions (32 Bits) Adding Constants Adding Using Address Registers 28 28 36 38 40 44 46 60 64 70 72 76 78 88 90 Comparison Instructions with Integers (16 Bits) Comparison Instructions with Integers (32 Bits) Comparison Instructions with Real Numbers (32 Bits) Shift Instructions Rotate Instructions Accumulator Transfer Instructions, Incrementing and Decrementing Program Display and Null Operation Instructions Data Type Conversion Instructions Forming the Ones and Twos Complements Block Call Instructions Block End Instructions Exchanging Shared Data Block and Instance Data Block Jump Instructions Instructions for the Master Control Relay (MCR) 122 124 Alphabetical Index of Instructions 162 126 128 132 134 136 138 142 144 148 150 152 160 Convention: In the following, the CPU 312 IFM is called CPU 312* In the following, the CPU 314 IFM is called CPU 314* In the following, the CPU 315-2 DP is called CPU 315-2 In the following, the CPU 316-2 DP is called CPU 316-2 98 102 104 106 108 110 112 114 116 118 120 S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 Addresses Identifiers and Parameter Ranges Addresses Identifiers and Parameter Ranges Address Identifiers and Parameter Ranges Addr ID Q QB Q QW Q QD Q Parameter Ranges 312* 313 314 314* 315/315–2/ 316–2 318-2 Description D i ti 0.0 to 2047.71 Output bit (in PIQ) 0.0 to 31.7 0.0 to 127.7 0.0 to 123.7 0.0 to 127.7 124.7 to 127.7 – 124.0 to 127.7 – – integrated outputs to 31 to 127 to 123 to 127 to 20471 Output byte (in PIQ) 124 to 127 – 124 to 127 – – integrated outputs 20461 Output word in (PIQ) integrated outputs to 30 to 126 to 122 to 126 to 124 to 126 – 124 to 126 – – to 28 to 124 to 120 to 124 to 20441 124 – 124 – – integrated outputs Output double word (in PIQ) B – – – Byte with general registerindirect addressing W – – – Word with general registerindirect addressing D – – – Double word with general register-indirect addressing 0.0 to 8191.7 0.0 to 8191.7 0.0 to 65533.7 Data bit in data block DBX DB to 63 to 127 to 127 to 2047 Data block DBB to 6143 to 8191 to 8191 to 65533 Data byte in DB DBW to 6142 to 8190 to 8190 to 65532 Data word in DB DBD to 6140 to 8188 to 8188 to 65530 Data double word in DB PIQ is preset to 256 byte S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 Addresses Identifiers and Parameter Ranges Addr ID Parameter Ranges 312* DIX DI Addresses Identifiers and Parameter Ranges 313 314 314* 0.0 to 8191.7 Description 315/315-2/ 316-2 318-2 0.0 to 8191.7 0.0 to 65533.7 Data bit in instance DB to 63 to 127 to 127 to 2047 Instance data block DIB to 6143 to 8191 to 8191 to 65533 Data byte in instance DB DIW to 6142 to 8190 to 8190 to 65532 Data word in instance DB DID to 6140 to 8188 to 8188 to 65530 Data double word in instance DB I 0.0 to 31.7 0.0 to 127.7 0.0 to 123.7 0.0 to 127.7 0.0 to 2047.7 124.0 to 127.7 – 124.0 to 127.7 – – integrated inputs to 31 to 127 to 123 to 127 to 2047 Input byte (in PII) 124 to 127 – 124 to 127 – – integrated inputs to 30 to 127 to 122 to 126 to 2046 Input word (in PII) 124 to 126 – 124 to 126 – – integrated inputs to 28 to 124 to 120 to 124 to 2044 124 – 124 – – 0.0 to 255.7 0.0 to 255.7 0.0 to 8191.7 LB to 255 to 255 to 8191 Local data byte LW to 254 to 254 to 8190 Local data word LD to 252 to 252 to 8188 Local data double word IB IW ID L Input bit (in PII) Input double word (in PII) integrated inputs Local data bit PII is preset to 256 byte Local data area is preset to 4096 byte S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 Addresses Identifiers and Parameter Ranges Addr ID M Addresses Identifiers and Parameter Ranges Parameter Ranges 312* 313 314 314* 315/315-2/ 316-2 318-2 Description 0.0 to 127.7 0.0 to 255.7 0.0 to 255.7 0.0 to 1023.0 MB to 127 to 255 to 255 to 1023 Bit memory byte MW to 126 to 254 to 254 to 1022 Bit memory word MD to 124 to 252 to 252 to 1020 Bit memory double word S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 Bit memory bit Addresses Identifiers and Parameter Ranges Addresses Identifiers and Parameter Ranges Parameter Ranges Addr ID PQB Q 318–2 313 314 314* 315 315-2/ 316–2 to 31 to 31 to 767 to 751 to 767 to 1023 to 8191 Peripheral p output p byte y (direct I/O access) to 766 to 750 to 766 to 1022 to 8190 Peripheral output word (direct I/O access) to 764 to 748 to 764 to 1020 to 8188 Peripheral output double word (direct I/O access) to 767 to 751 to 767 to 1023 to 8191 Peripheral p input p byte y (direct I/O access) to 766 to 750 to 766 to 1022 to 8190 Peripheral p input p word (direct I/O access) to 764 to 748 to 764 to 1020 to 8188 Peripheral input double word (direct I/O access) to 127 to 511 Timer to 63 to 511 Counter 124 PQW PQD PIB 256 to 383 256 to 383 to 30 to 30 256 to 382 256 to 382 to 28 to 28 256 to 380 256 to 380 to 31 to 31 124 to 125 PIW 256 to 383 256 to 383 to 30 to 30 124 PID Description 312* 256 to 382 256 to 382 to 28 to 28 256 to 380 256 to 380 T to 63 Z to 31 to 127 to 35 to 63 Parameter – – Instruction addressed via parameter B#16# W#16# DW#16# – – Byte Word Double word hexadecimal S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 Addresses Identifiers and Parameter Ranges Addr ID Addresses Identifiers and Parameter Ranges Parameter Ranges 312* 313 314 314* 315/315–2, 316 318-2 Description D# – – IEC data constant L# – – 32-bit integer constant P# – – Pointer constant S5T# – – S5 time constant (16 bits) Time constant (16/32 bits) T# – TOD# – – IEC time constant C# – – Counter constant (BCD–codiert) 2# – – Binary constant B (b1,b2) B (b1,b2, b3,b4) – – Constant, or Byte 10 for loading of S5 timers T#1D_5H_3M_1S_2MS S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 11 Abbreviations and Mnemonics Abbreviations and Mnemonics Abbreviations and Mnemonics The following abbreviations and mnemonics are used in the Instruction List: Abbreviations Description Example Abbreviations Description Example k8 8-bit constant 32 f Timer–/Zähler–Nr k16 16-bit constant 62 531 g Operandenbereich k32 32-bit constant 127 624 IB, QB, PIB, MB, LB, DBB, DIB i8 8-bit integer –155 h Operandenbereich IW, QW, PIW, MW, LW, DBW, DIW i16 16-bit integer +6523 i Operandenbereich i32 32-bit integer –2 222 222 ID, QD, PID, MD, LD, DBD, DID m P#x.y (pointer) P#240.3 r Baustein–Nr 10 n Binary constant 1001 1100 p Hexadecimal constant EA12 q Real number (32-bit floating-point number) 12.34567E+5 LABEL Symbolic jump address (max characters) DEST a Byteadresse b Bitadresse x.1 c Operandenbereich I, Q, M, L, DBX, DIX 12 S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 13 Registers Registers Registers S Area-internal address ACCU1 and ACCU2 (32 Bits) The accumulators are registers for processing bytes, words or double words The operands are loaded into the accumulators, where they are logically gated The result of the logic operation (RLO) is in ACCU1 00000000 00000bbb bbbbbbbb bbbbbxxx S Area-crossing address 10000yyy 00000bbb bbbbbbbb bbbbbxxx Legend: CPU 318–2: also ACCU3 and ACCU4 Accumulator designations: b Byte address x Bit number y Area identifier (see section “Examples of Addressing”) Bits ACCU ACCUx (x = to 4) Bits to 31 ACCUx-L Bits to 15 ACCUx-H Bits 16 to 31 ACCUx-LL Bits to ACCUx-LH Bits to 15 ACCUx-HL Bits 16 to 23 ACCUx-HH Bits 24 to 31 Status Word (16 Bits) The status word bits are evaluated or set by the instructions The status word is 16 bits long Bit Assignment FC RLO Result of (previous) logic operation STA Status * OR Or * Address Registers AR1 and AR2 (32 Bits) OS Stored overflow The address registers contain the area-internal or area-crossing addresses for instructions using indirect addressing The address registers are 32 bits long OV Overflow CC Condition code CC Condition code BR 15 Unassigned The area-internal and/or area-crossing addresses have the following syntax: Description First check bit * Binary result – * Bit cannot be evaluated in the user program with the L STW instruction since it is not updated at program runtime 14 S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 15 Examples of Addressing Examples of Addressing Examples of Addressing Addressing Examples Description Direct Addressing Addressing Examples Description Direct Addressing L +27 Load 16-bit integer constant “27” into ACCU1 A I 0.0 ANDing of input bit 0.0 L L#–1 Load 32-bit integer constant “–1” into ACCU1 L IB Load input byte into ACCU1 L IW Load input word into ACCU1 L 2#1010101010101010 Load binary constant into ACCU1 L ID Load input double word into ACCU1 L DW#16#A0F0_BCFD Load hexadecimal constant into ACCU1 Indirect Addressing of Timers/Counters L ’END’ Load ASCII character into ACCU1 SP T [LW 8] Start timer; the timer number is in local word L T#500 ms Load time value into ACCU1 CU C [LW 10] Start counter; the counter number is in local data word 10 L C#100 Load count value into ACCU1 L B#(100,12) Load 2-byte constant L B#(100,12,50,8) Load 4-byte constant L P#10.0 Load area-internal pointer into ACCU1 L P#E20.6 Load area-crossing pointer into ACCU1 L –2.5 Load real number into ACCU1 L D#1995–01–20 Load date L TOD#13:20:33.125 Load time of day 16 S7-300 Instruction List EWA 4NEB 710 6087-02 Area-Internal Memory-Indirect Addressing A I [LD 12] Example: L P#22.2 T LD 12 A I [LD 12] AND operation: The address of the input is in local data double word 12 as pointer A I [DBD 1] AND operation: The address of the input is in data double word of the DB as pointer A Q [DID 12] AND operation: The address of the output is in data double word 12 of the instance DB as pointer A Q [MD 12] AND operation: The address of the output is in memory marker double word 12 of the instance DB as pointer S7-300 Instruction List EWA 4NEB 710 6087-02 17 List of Instructions Instruction List of Instructions Typical Execution Time in ms Length Address Identifier in Words Description Indirect Addressing Direct Addressing 312* 313 314 314* 315 315-2 316-2 1/22 2 2.9 1.6 1.5 BR CC CC OV OS OR STA RLO FC Instruction depends on: – – – – – – – – – Instruction affects: – – – – – – – – – OPN DB q DI q Parameter Status word for: 146 Open: Data block Instance data block Data block using parameters OPN 318-2 312* 313 314 314* 315 315-2 316-2 0.3 4.0+ 1.4+ 2.6+ 318-2 0.3+ Plus time required for loading the address of the instruction (see page 21) With direct instruction addressing Block No > 255 S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 147 List of Instructions List of Instructions Block End Instructions Instruction Address Identifier BE – BEU – Status word for: Length in Words Description End block Typical Execution Time in ms 312*/313 314/314* 315/315-2/ 316-2 318-2 4.9 4.1 2.8 2.0 End block unconditionally – – – – BR CC CC OV OS OR STA RLO FC Instruction depends on: – – – – – – – – – Instruction affects: – – – – 0 – BEC – Status word for: BE, BEU End block conditionally if RLO = “1” 4.4 3.2 2.2 BR CC CC OV OS OR STA RLO FC Instruction depends on: – – – – – – – Yes – Instruction affects: – – – – Yes 1 148 BEC 5.9 S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 149 List of Instructions List of Instructions Exchanging Shared Data Block and Instance Data Block Exchanging the two current data blocks The current shared data block becomes the current instance data block, and vice versa The condition code bits are not affected Instruction CDB 150 Address Identifier – Description Exchange shared data block and instance data block Length in Words S7-300 Instruction List EWA 4NEB 710 6087-02 Typical Execution Time in ms 312*/313 314/314* 315/315-2/ 316-2 1.0 0.3 0.4 S7-300 Instruction List EWA 4NEB 710 6087-02 318-2 151 List of Instructions List of Instructions Jump Instructions Jumping as a function of conditions With 8–bit operands the jump width is between –128 and +127 In the case of 16–bit operands, the jump width lies between –32768 and –129 (+128 and +32767) Instruction Address Identifier Note: Please note for S7–300 CPU programs that the jump destination always (not for 318–2) forms the beginning of a Boolean logic string in the case of jump instructions The jump destination must not be included in the logic string Length in Words Description Typical Execution Time in ms 312*/313 JU LABEL Status word for: 1/2 Jump unconditionally JU 315/315-2/ 316-2 314/314* 1.8 1.7 318-2 1.8 0.5 BR CC CC OV OS OR STA RLO FC Instruction depends on: – – – – – – – – – Instruction affects: – – – – – – – – – JC LABEL Jump if RLO = “1” 1/2 JCN LABEL Jump if RLO = “0” Status word for: JC, JCN 2.3 2.0 1.5 0.5 2.6 2.3 1.6 0.5 BR CC CC OV OS OR STA RLO FC Instruction depends on: – – – – – – – Yes – Instruction affects: – – – – – 1 JCB LABEL Jump if RLO = “1” Save the RLO in the BR bit 2.9 2.2 1.8 0.5 JNB LABEL Jump if RLO = “0” Save the RLO in the BR bit 2.9 2.4 1.8 0.5 Status word for: JCB, JNB Instruction depends on: Instruction affects: 152 BR CC CC OV OS OR STA RLO FC – – – – – – – Yes – Yes – – – – 1 word long for jump widths between –128 and +127 S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 153 List of Instructions Instruction List of Instructions Address Identifier JBI LABEL JNBI LABEL Status word for: Jump if BR = “1” Jump if BR = “0” Instruction affects: Status word for: 312*/313 314/314* 315/315-2/ 316-2 318-2 2.3 2.1 1.5 0.5 JBI, JNBI LABEL Typical Execution Time in ms Instruction depends on: JO Length in Words Description 2.1 1.5 0.5 CC CC OV OS OR STA RLO FC Yes – – – – – – – – – – – – – – 1/2 Jump on stored overflow (OV = “1”) 2.3 2.1 1.5 0.5 BR CC CC OV OS OR STA RLO FC Instruction depends on: – – – Yes – – – – – Instruction affects: – – – – – – – – – JOS LABEL Status word for: JO 2.3 BR Jump on stored overflow (OS = “1”) 2.6 2.2 1.6 0.5 BR CC CC OV OS OR STA RLO FC Instruction depends on: – – – – Yes – – – – Instruction affects: – – – – – – – – 154 JOS word long for jump widths between –128 and +127 S7-300 Instruction List EWA 4NEB 710 6087-02 S7-300 Instruction List EWA 4NEB 710 6087-02 155 List of Instructions Instruction List of Instructions Address Identifier Length in Words Description Typical Execution Time in ms 312*/313 314/314* 315/315-2/ 316-2 318-2 2.8 2.3 1.8 0.5 JUO LABEL Jump if “unordered instruction” (CC 1=1 and CC 0=1) JZ LABEL Jump if result=0 (CC 1=0 and CC 0=0) 1/2 2.7 2.2 1.7 0.5 JP LABEL Jump if result>0 (CC 1=1 and CC 0=0) 1/2 2.7 2.4 1.8 0.5 JM LABEL Jump if result[...]... time: 5.3 ms + 2.0 ms = 7.3 ms 26 S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 27 List of Instructions List of Instructions List of Instructions page 16), you must add the time required for loading the address of the particular instruction to the execution times listed (see page 21) This chapter contains the complete list of S7- 300 instructions The descriptions... execution time (see Table on following page) The pages that follow contain examples for calculating the instruction run time for the various indirectly addressed instructions 20 S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 21 Execution Times with Indirect Addressing Execution Times with Indirect Addressing Examples of Calculations (for the CPU 314) You will... page 21) Address is in Execution Time in ms Bit memory area M Word Double word 0.7 2.3 Data block DB/DI Word Double word 2.8 3.9 22 S7- 300 Instruction List EWA 4NEB 710 6087-02 Indirect Addressing Time for AI 2.0+ : Total execution time: 3.9 ms + 2.0 ms = 5.9 ms S7- 300 Instruction List EWA 4NEB 710 6087-02 23 Execution Times with Indirect Addressing Execution Times with Indirect Addressing Calculating... the input addressed in this way (you will find the execution time in the tables in the chapter entitled “List of Instructions”) Typical Execution Time in ms Direct Addressing 3.9 S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 25 Execution times with Indirect Addressing Execution times with Indirect Addressing Execution Time for Addressing Via Parameters Example:... “pointer value in AR1+ P#32.3” 18 LAR1 P#8.2 A I [AR1,P#10.2] S7- 300 Instruction List EWA 4NEB 710 6087-02 Input 18.4 is addressed (by adding the byte and bit addresses) S Example for sum of bit addressesu7: L MD 0 Random pointer, e.g P#10.5 LAR1 A I [AR1,P#10.7] Result: Input 21.4 is addressed (by adding the byte and bit addresses with carry) S7- 300 Instruction List EWA 4NEB 710 6087-02 19 Execution Times... Indirect Addressing 1 Direct Addressing Words Plus time required for loading the address of the instruction (see page 21) With direct instruction addressing Adress area 0 to 127 S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 29 List of Instructions InIn struction List of Instructions Typical Execution Time in ms Length Address Identifier AN I/Q M L DBX DIX a.b... Indirect Addressing 1 Direct Addressing Words Plus time required for loading the address of the instruction (see page 21) With direct instruction addressing Adress area 0 to 127 S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 31 List of Instructions InIn struction List of Instructions Typical Execution Time in ms Length Address Identifier O I/Q M L DBX DIX a.b... Yes 1 1 2 32 O, ON Indirect Addressing 1 Direct Addressing Words Plus time required for loading the address of the instruction (see page 21) With direct instruction addressing S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 33 List of Instructions InIn struction List of Instructions Typical Execution Time in ms Length Address Identifier X Description in Indirect... Instruction depends on: – – – – – – – Yes Yes Instruction affects: – – – – – 0 Yes Yes 1 1 34 X, XN Plus time required for loading the address of the instruction (see page 21) S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 35 List of Instructions List of Instructions Bit Logic Instructions with Parenthetical Expressions Saving the BR, RLO and OR bits and a... the current RLO in the processor ) Instruction depends on: Instruction affects: BR 1 3.3 1.7 1.9 0.1 BR CC 1 CC 0 OV OS OR STA RLO FC – – – – – – – Yes – Yes – – – – Yes 1 Yes 1 S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 37 List of Instructions List of Instructions ORing of AND Operations The ORing of AND operations is implemented according to the rule: ... 316-2 DP is called CPU 316-2 98 102 104 106 108 110 112 114 116 118 120 S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 Addresses Identifiers and Parameter... 8188 to 8188 to 65530 Data double word in DB PIQ is preset to 256 byte S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 Addresses Identifiers and Parameter... data bit PII is preset to 256 byte Local data area is preset to 4096 byte S7- 300 Instruction List EWA 4NEB 710 6087-02 S7- 300 Instruction List EWA 4NEB 710 6087-02 Addresses Identifiers and Parameter

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  • Title

  • Contents

  • Address Identifiers and Parameter Ranges

  • Abbreviations and Mnemonics

  • Registers

  • Examples of Addressing

  • Execution Times with Indirect

  • List of Instructions

    • Bit Logic Instructions with Parenthetical

    • ORing of AND Operations

    • Logic Instructions with Timers and

    • Word Logic Instructions with the Contents of Accumulator 1

    • Evaluating Conditions Using AND, OR and EXCLUSIVE OR

    • Edge- Triggered Instructions

    • Setting/ Resetting Bit Addresses

    • Instructions Directly Affecting the RLO

    • Timer Instructions

    • Counter Instructions

    • Load Instructions

    • Load Instructions for Timers and Counters

    • Transfer Instructions

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