AN576 Techniques to Disable Global Interrupts Author: Mark Palmer Microchip Technology Inc Contributions by Martin Burghardt Manager Applications (Central Europe) INTRODUCTION This application note discusses four methods for disabling global interrupts The method best suited for the application may then be used All discussion will be specific to the PIC16CXXX family of products, but these concepts are also applicable to the PIC17C42, and are shown in the even numbered examples Note that the PIC17C42’s global interrupt bit is called GLINTD and has an inverse sense compared to the GIE bit of the PIC16CXXX family To disable all interrupts, either the Global Interrupt Enable (GIE) bit must be cleared or all the individual interrupt enable bits must be cleared An issue arises when an instruction clears the GIE bit and an interrupt occurs "simultaneously" For example, when a program executes the instruction BCF INTCON, GIE (at address PC), there is a possibility that an interrupt will occur during this instruction If an interrupt occurs dur- EXAMPLE 1: LOOP BCF BTFSC GOTO : : BSF EXAMPLE 2: LOOP : BSF BTFSS GOTO : : BCF ing this instruction, the program would complete execution of this instruction, and then immediately branch to the user’s interrupt service routine This occurs because the GIE bit was not clear (disabled) when the interrupt occurred Normally at the end of the interrupt service routine is the RETFIE instruction This instruction causes the program to return to the instruction at PC + 1, but also sets the GIE bit (enabled) Therefore the GIE bit is not cleared as expected, and unintended program execution may occur One method to ensure that the GIE bit is cleared is shown in Example and Example 2, as well as in the PIC16CXXX data sheets This method tests the state of the GIE bit, after clearing, to ensure that it was not accidentally set in the user’s interrupt service routine by the RETFIE instruction If the GIE bit was accidentally set, the program branches back to the instruction that clears the GIE bit In this method, the time to ensure that the GIE bit is cleared is indeterminate Depending on the frequency of the enabled interrupts during this code segment, unexpected delays into the following code segment may occur For some applications, this may be undesirable The following three methods address this issue CLEARING THE GIE BIT (DISABLING INTERRUPTS, METHOD 1, PIC16CXXX) INTCON, GIE INTCON, GIE LOOP ; ; ; ; Disable Global Interrupt Global Interrupt Disabled? NO, try again YES, continue with program flow INTCON, GIE ; Re-enable Global Interrupt SETTING THE GLINTD BIT (DISABLING INTERRUPTS, METHOD 1, PIC17C42) CPUSTA, GLINTD ; Disable Global Interrupt CPUSTA, GLINTD ; Global Interrupt Disabled? LOOP ; NO, try again ; YES, continue with program flow CPUSTA, GLINTD ; Re-enable Global Interrupt  1997 Microchip Technology Inc DS00576B-page 5-99 AN576 The second method is to disable the individual interrupt enable bits If it is known which bits are enabled at this point, it can easily be done Example and Example show the disabling of interrupts, where it is known which sources are enabled (some peripheral interrupts and the T0CKI pin interrupt) EXAMPLE 3: : MOVLW ANDWF : : : MOVLW IORWF : CLEARING KNOWN INDIVIDUAL INTERRUPT ENABLE BITS (METHOD 2, PIC16CXXX) b’10011111’ INTCON, F ; Disable Peripheral and T0CKI pin interrupts, ; All other bits unchanged b’01100000’ INTCON, F ; Re-enable Peripheral and T0CKI pin interrupts, ; All other bits unchanged EXAMPLE 4: : MOVLW ANDWF : : : MOVLW IORWF : This method also requires the same number of instructions for the disabling/enabling of interrupts, as method 1, but requires a knowledge of which individual interrupt enable bits need to be disabled and (more importantly) re-enabled The major advantage of this method is that it can minimize the time delay entering the code segment which follows the point where interrupts are disabled CLEARING KNOWN INDIVIDUAL INTERRUPT ENABLE BITS (METHOD 2, PIC17C42) b’11110011’ INTSTA, F ; Disable Peripheral and T0CKI pin interrupts, ; All other bits unchanged b’00001100’ INTSTA, F ; Re-enable Peripheral and T0CKI pin interrupts, ; All other bits unchanged DS00576B-page 5-100  1997 Microchip Technology Inc AN576 Method can be used if the states of the individual interrupt enable bits are unknown A temporary byte of data RAM is required to store the value of the INTCON register This method is shown in Example and Example EXAMPLE 5: This method also requires more instructions for the disabling/enabling of interrupts than in method or method 2, and also a byte of data RAM to temporarily store the value of the INTCON register The major advantage of this method is that it minimizes the time delay into the code segment which follows the point where interrupts are disabled CLEARING THE INDIVIDUAL INTERRUPT ENABLE BITS (METHOD 3, PIC16CXXX) : MOVF MOVWF MOVLW ANDWF : : : MOVF IORWF : INTCON, W S_INTCON b’10000111’ INTCON, F ; ; ; ; S_INTCON, W INTCON, F ; Restore the INTCON register ; EXAMPLE 6: : MOVPF MOVLW ANDWF : : : MOVFP IORWF : Move the value in INTCON to a shadow register Disable all individual interrupts, All other bits unchanged CLEARING THE INDIVIDUAL INTERRUPT ENABLE BITS (METHOD 3, PIC17C42) INTSTA, S_INTSTA b’11110000’ INTSTA, F ; Move the value in INTSTA to a shadow register ; Disable all individual interrupts, ; All other bits unchanged S_INTSTA, W INTSTA, F ; Restore the INTSTA register ;  1997 Microchip Technology Inc DS00576B-page 5-101 AN576 The final method is to use a RAM location to “shadow” the value of the GIE bit This shadow bit can then be used in the interrupt service routine to determine which return instruction to use That is, either the RETURN or the RETFIE (which enables the GIE bit) instruction Example and Example show this implementation, which require that a general purpose bit be available to hold the “shadow“ GIE value In these examples, the shadow GIE (S_GIE) bit is contained in the register FLAG_REG If an interrupt occurs during the clearing of the shadow GIE, the interrupt is responded to At the end of the interrupt service routine, the shadow GIE bit is cleared so the RETURN instruction is executed The GIE bit remains disabled and program execution returns to the instruction which tries to clear the GIE bit EXAMPLE 7: (disable) No interrupts can occur during this instruction since the GIE bit was not re-enabled after the interrupt service routine This method also requires more instructions for the disabling/enabling of interrupts than in method or method 2, and a single bit of data RAM to temporarily store the value of the desired GIE value, and increases the interrupt service routine execution time by one instruction cycle, for most occurrences of interrupts (two cycles worst case) The major advantage of this method is that it minimizes the time delay into the code segment which follows the point where interrupts are disabled Also, the individual interrupt enable bits need not be modified THE “SHADOW” GIE BIT (METHOD 4, PIC16CXXX) : org 0x004 INT_SERVICE_ROUTINE : : BTFSC FLAG_REG, S_GIE RETFIE RETURN END_INT_SERVICE_ROUTINE ; MAIN: : : BCF FLAG_REG, S_GIE BCF INTCON, GIE : : : BSF FLAG_REG, S_GIE BSF INTCON, GIE : : END EXAMPLE 8: ; Is the S_GIE bit enabled? ; YES, the GIE should be enabled ; NO, the GIE should be disabled ; Clear the shadow GIE bit ; Disable interrupts by clearing the GIE bit ; Set the shadow GIE bit ; Enable interrupts by setting the GIE bit THE “SHADOW” GLINTD BIT (METHOD 4, PIC17C42) : org 0x004 INT_SERVICE_ROUTINE : : BTFSS FLAG_REG, S_GLINTD RETFIE RETURN END_INT_SERVICE_ROUTINE ; MAIN: : : BSF FLAG_REG, S_GLINTD BSF CPUSTA, GLINTD : : : BCF FLAG_REG, S_GLINTD BCF CPUSTA, GLINTD : : END DS00576B-page 5-102 ; Is the S_GLINTD bit enabled? ; YES, the GLINTD should be enabled ; NO, the GLINTD should be disabled ; Set the shadow GLINTD bit ; Disable interrupts by setting the GLINTD bit ; Clear the shadow GLINTD bit ; Enable interrupts by clearing the GLINTD bit  1997 Microchip Technology Inc AN576 CONCLUSION In conclusion, different methods exist to ensure that all interrupts are disabled The requirement(s) of the application determines which of the methods is the best fit A comparison of the different methods is shown in Table TABLE 1: COMPARISON OF DIFFERENT METHODS Cycle Delay (TCY) Program Memory Data Memory Best Case Worst Case Method words * N  Indeterminate Method 2 words * N  1 + TISR Method - PIC16CXXX words * N byte 3 + TISR words * N byte 2 + TISR words * N + words bit 1† + (TISR + 2) - PIC17C42 Method Legend: N TISR † Number of occurrences to disable / re-enable interrupts Time to execute the interrupt service routine This method increases the interrupt service routine time (TISR) by cycle for most occurrences (2 cycles worst case)  1997 Microchip Technology Inc DS00576B-page 5-103 AN576 NOTES: DS00576B-page 5-104  1997 Microchip Technology Inc  ... follows the point where interrupts are disabled CLEARING KNOWN INDIVIDUAL INTERRUPT ENABLE BITS (METHOD 2, PIC17C42) b’11110011’ INTSTA, F ; Disable Peripheral and T0CKI pin interrupts, ; All other... data RAM to temporarily store the value of the INTCON register The major advantage of this method is that it minimizes the time delay into the code segment which follows the point where interrupts. .. S_INTCON, W INTCON, F ; Restore the INTCON register ; EXAMPLE 6: : MOVPF MOVLW ANDWF : : : MOVFP IORWF : Move the value in INTCON to a shadow register Disable all individual interrupts, All other