VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY UNIVERSITY OF SCIENCE NGUYỄN THỊ ĐÊ LOW POWER DESIGN FOR VLSI Specialization: Electronic Engineering – Microelectronic Major Code: 60 52 70 MASTER DEGREE THESIS ELECTRONIC ENGINEERING – MICROELECTRONICS SUPERVISOR ASSOC PROF DR NGUYỄN HỮU PHƯƠNG HO CHI MINH CITY, 2010 Table of Contents TABLE OF CONTENTS LIST OF FIGURES LIST OF TABLES CHAPTER I: INTRODUCTION 1.1 Rationale 1.2 Scope 1.3 Structure of the Research CHAPTER II: TECHNIQUES TO REDUCE POWER DISSIPATION 2.1 Sources of Power Dissipation 2.1.1 Static Dissipation 10 2.1.2 Dynamic Dissipation 12 2.2 Techniques to Reduce Power Dissipation 13 2.2.1 Dynamic Power Reduction 13 2.2.2 Static Power Reduction 14 CHAPTER III: MATLAB SIMULATION OF POWER DISSIPATION 18 3.1 MatLab 18 3.1.1 Why choose MatLab? 18 3.1.2 A Short Introduction to Matlab 18 3.2 Relationship between Power Dissipation and Related Circuit Parameters 20 3.2.1 Static Power Dissipation 20 3.2.1.1 Relationship between Static Power and Static Current 21 3.2.1.2 Relationship between Static Power and Supply Voltage 22 3.2.2 Dynamic Power Dissipation 23 3.2.2.1 Relationship between Dynamic Power and Activity Switching 23 3.2.2.2 Relationship between Dynamic Power and Load Capacitance 24 Nguyễn Thị Đê 3.2.2.3 Relationship between Dynamic Power and Supply Voltage 25 3.2.2.4 Relationship between Dynamic Power and Frequency 26 CHAPTER IV: LOW POWER DESIGN OF A SIMPLE LOGIC CIRCUIT 28 4.1 1-Bit Magnitude Comparator Circuit 28 4.1.1 Principle 28 4.1.2 Truth Table 28 4.2 Low Power Design 29 4.2.1 Low Power Design at Circuit Level 29 4.2.1.1 Purpose 29 4.2.1.2 Design Basic 29 4.2.1.3 Design Implementation 35 4.2.2 Low Power Design at Layout Level 55 4.2.2.1 Purpose 55 4.2.2.2 Layout Implementation 55 CHAPTER V: CONCLUSION 93 BIBLIOGRAPHY 94 Nguyễn Thị Đê List of Figures Figure 2.1: CMOS inverter model for static power dissipation evaluation 11 Figure 2.2: A Variable-Threshold CMOS (VTCMOS) inverter circuit 15 Figure 2.3: Generic structure of a Multiple-Threshold CMOS (MTCMOS) 16 Figure 3.1: Relationship between Static Power and Static Current 26 Figure 3.2: Relationship between Static Power and Supply Voltage 27 Figure 3.3: Relationship between Dynamic Power and Activity Switching 28 Figure 3.4: Relationship between Dynamic Power and Load Capacitance 29 Figure 3.5: Relationship between Dynamic Power and Supply Voltage 30 Figure 3.6: Relationship between Dynamic Power and Frequency 31 Figure 4.1: General operation using switch logic 30 Figure 4.2: Operation of the CMOS NOT gate 30 Figure 4.3: Operation of the 2-input NAND gate 31 Figure 4.4: Operation of the 2-input NOR gate 31 Figure 4.5: Logic formation using nFET in the CMOS logic gate 32 Figure 4.6: Logic formation using pFET in the CMOS logic gate 33 Figure 4.7: XOR and XNOR gates 34 Figure 4.8: XOR and XNOR gates with complementary structuring 35 Figure 4.9: Design_1 Schematic Circuit 36 Figure 4.10: Schematic Circuit using CMOS Transistors 37 Figure 4.11: Waveform of Signals 38 Figure 4.12: Static Power Dissipation 39 Figure 4.13: Dynamic Power Dissipation 41 Figure 4.14: Average Power Dissipation 42 Figure 4.15: Supply Current 43 Figure 4.16: Supply Power (VI) 44 Figure 4.17: Average Supply Power (VI) 45 Nguyễn Thị Đê Figure 4.18: Design_2 Schematic Circuit 46 Figure 4.19: Schematic Circuit Using CMOS Transistors 47 Figure 4.20: Waveform of Signals 48 Figure 4.21: Static Power Dissipation 49 Figure 4.22: Dynamic Power Dissipation 50 Figure 4.23: Average Power Dissipation 51 Figure 4.24: Supply Current 52 Figure 4.25: Supply Power (VI) 53 Figure 4.26: Average Supply Power (VI) 54 Figure 4.27: Layout_1 View 56 Figure 4.28: Extracted View 57 Figure 4.29: Extracted Parasitic Capacitors 58 Figure 4.30: Analog_Extracted View 59 Figure 4.31: LVS Verification 60 Figure 4.32: Waveform of Signals 61 Figure 4.33: Static Power Dissipation 62 Figure 4.34: Dynamic Power Dissipation 63 Figure 4.35: Average Power Dissipation 64 Figure 4.36: Supply Current 65 Figure 4.37: Supply Power (VI) 66 Figure 4.38: Average Supply Power (VI) 67 Figure 4.39: Layout_2 View 68 Figure 4.40: Extracted View 69 Figure 4.41: Extracted Parasitic Capacitors 70 Figure 4.42: Analog_Extracted View 71 Figure 4.43: LVS Verification 72 Figure 4.44: Waveform of Signals 73 Figure 4.45: Static Power Dissipation 74 Figure 4.46: Dynamic Power Dissipation 75 Nguyễn Thị Đê Figure 4.47: Average Power Dissipation 76 Figure 4.48: Supply Current 77 Figure 4.49: Supply Power (VI) 78 Figure 4.50: Average Supply Power (VI) 79 Figure 4.51: Layout_3 View 80 Figure 4.52: Extracted View 81 Figure 4.53: Extracted Parasitic Capacitors 82 Figure 4.54: Analog_Extracted View 83 Figure 4.55: LVS Verification 84 Figure 4.56: Waveform of Signals 85 Figure 4.57: Static Power Dissipation 86 Figure 4.58: Dynamic Power Dissipation 87 Figure 4.59: Average Power Dissipation 88 Figure 4.60: Supply Current 89 Figure 4.61: Supply Power (VI) 90 Figure 4.62: Average Supply Power (VI) 91 Nguyễn Thị Đê List of Tables Table 3.1: Useful operations, functions and constants in Matlab 19 Table 3.2: Useful plotting commands in Matlab 200 Table 4.1: Truth table for 1-bit magnitude comparator circuit 29 Table 4.2: Summary Table………………………………………………………………92 Nguyễn Thị Đê CHAPTER I INTRODUCTION This introductory chapter emphasizes the importance of VLSI low power design for modern electronic devices and systems, and presents the scope and the structure of my thesis 1.1 Rationale Nowadays, electronic circuits and systems must have as low power dissipation as possible, especially in the field of mobile communications In these devices, if have no techniques to reduce power consumption then, they will suffer from either a very short battery life or a very heavy battery pack Even in the case of non-portable systems, reductions in power consumption are also important These systems often run hot and this causes failure mechanisms We must cost for cooling and packaging Therefore, it is essential to have the peak power under control [9][13][16] 1.2 Scope The main study of the thesis is to examine the techniques of reducing CMOS power dissipation; obtaining the relationship between power dissipation with related circuit parameters; and how to design for power dissipation optimization up to layout level of a simple digital circuit A 1-bit magnitude comparator circuit will be used as an example of a digital circuit for design and estimating power dissipation The design is implemented in Nguyễn Thị Đê 180nm technology using Cadence software Even rather simple but this illustrative design includes many aspects of low power design 1.3 Structure of the Research The remainder of this research comprises four chapters  Chapter II: Techniques to Reduce Power Dissipation  Chapter III: MatLab Simulation of Power Dissipation  Chapter IV: Low Power Design of A Simple Logic Circuit  Chapter V: Conclusion Nguyễn Thị Đê CHAPTER II TECHNIQUES TO REDUCE POWER DISSIPATION This chapter discusses quantitatively the static and dynamic power dissipation in CMOS circuit, and techniques to reduce them 2.1 Sources of Power Dissipation In [14], the instantaneous power P(t) drawn from the power supply is proportional to the instantaneous supply current iDD(t) and the supply voltage VDD (assumed constant ) P(t) = iDD(t).VDD (2.1) The average power over some time interval T is = ∫ ( ) (2.2) Power dissipation in CMOS circuit comes from two components:  Static dissipation due to o Sub-threshold conduction through OFF transistors o Tunneling current through gate oxide o Leakage through reverse-bias diodes  Dynamic dissipation due to o Charging and discharging of load capacitances Nguyễn Thị Đê 82  Extracted Parasitic Capacitors Figure 4.53: Extracted Parasitic Capacitors (A part of Extracted View is zoomed in to see extracted parasitic capacitors) Layout_3 has 42 parasitic capacitors Nguyễn Thị Đê 83  Analog_Extracted View Figure 4.54: Analog_Extracted View Nguyễn Thị Đê 84  Post_Layout Simulation  LVS Verification Figure 4.55: LVS Verification Nguyễn Thị Đê 85  Waveform of Signals Figure 4.56: Waveform of Signals  The waveform is result of simulating Analog_Extracted View (Layout_3) at VDD: 1.8V DC, Transient Analysis: 8n (Stop time), and stimulus: o Input A: Function: pulse, Type: Voltage, Voltage1: 0, Voltage2: 5, Rise time: 0.1n, Fall time: 0.1n, Pulse width: 1n, Period: 2n o Input B: Function: pulse, Type: Voltage, Voltage1: 0, Voltage2: 5, Rise time: 0.1n, Fall time: 0.1n, Pulse width: 2n, Period: 4n  Remark: Waveform of Signals matches the Truth table (Table 4.1) Nguyễn Thị Đê 86  Static Power Dissipation Figure 4.57: Static Power Dissipation  The waveform is result of measuring the instantaneous static power dissipation when _Extracted View (Layout_3) is simulated at VDD: 1.8V DC, Transient Analysis: 8n (Stop time), and stimulus: o Input A: OFF o Input B: OFF Nguyễn Thị Đê 87  Dynamic Power Dissipation Figure 4.58: Dynamic Power Dissipation  The waveform is result of measuring the instantaneous dynamic power dissipation when Analog_Extracted View (Layout_1) is simulated at VDD: 1.8V DC, Transient Analysis: 8n (Stop time), and stimulus: o Input A: Function: pulse, Type: Voltage, Voltage1: 0, Voltage2: 5, Rise time: 0.1n, Fall time: 0.1n, Pulse width: 1n, Period: 2n o Input B: Function: pulse, Type: Voltage, Voltage1: 0, Voltage2: 5, Rise time: 0.1n, Fall time: 0.1n, Pulse width: 2n, Period: 4n Nguyễn Thị Đê 88  Average Power Dissipation Figure 4.59: Average Power Dissipation  Average Power Dissipation value (in the Calculator window) is result of taking average of instantaneous power dissipation waveform at interval of simulation time (8ns) Nguyễn Thị Đê 89  Supply Current Figure 4.60: Supply Current  Above waveform is result of measuring instantaneous supply current, iDD, when Analog_Extracted View (Layout_3) is simulated at VDD: 1.8V DC, Transient Analysis: 8n (Stop time), and stimulus: o Input A: Function: pulse, Type: Voltage, Voltage1: 0, Voltage2: 5, Rise time: 0.1n, Fall time: 0.1n, Pulse width: 1n, Period: 2n o Input B: Function: pulse, Type: Voltage, Voltage1: 0, Voltage2: 5, Rise time: 0.1n, Fall time: 0.1n, Pulse width: 2n, Period: 4n  Below waveform is result of taking inversion of above waveform to obtain the positive instantaneous supply current Nguyễn Thị Đê 90  Supply Power (VI) Figure 4.61: Supply Power (VI)  The waveform is result of multiplying the positive instantaneous supply current by VDD (1.8V) to make instantaneous supply power p = V.i Nguyễn Thị Đê 91  Average Supply Power (VI) Figure 4.62: Average Supply Power (VI)  Average Supply Power (VI) value (in the Calculator window) is result of taking average of instantaneous supply power waveform at interval of simulation time (8ns)  Remark: o Ptotal = VDD.IDD ≈ Pstatic + P dynamic (for average power) o From the simulation result, we get the average power dissipation for Layout_3 is approximately 2.37x10 -4 W = 0.237mW Nguyễn Thị Đê 92  Conclusion o The Layout_3 has average power dissipation higher than two other layouts because it introduces more parasitic capacitances Besides the parasitic capacitances between interconnects on the first metal layer, is parasitic capacitances between the first and the second metal layers o The Layout_1 has average power dissipation higher than Layout_2 because the numbers of interconnects in it is more and thus it also introduces more parasitic capacitances o Layout_2 is considered as an optimal design Table 4.2: Summary Table Design_1 Design_2 Layout_1 Layout_2 Layout_3 Average power dissipation Number of Capacitors Nguyễn Thị Đê 0.12mW 0.099mW 0.16mW 0.14mW 0.237mW 37 34 42 93 CHAPTER V CONCLUSION Reducing the average power dissipation is one of the great challenges for many present and future electronic systems [16] Low power design requires the reduction of parasitic capacitances, activity factor, supply voltage, static current The relationship between power dissipation with related circuit parameters can be expressed quantitatively by mathematical equations, which can be simulated conveniently by MatLab The thesis also introduces several power dissipationreduction approaches through design and estimation the power dissipation of a 1-bit magnitude comparator circuit up to layout level The implemented results showed that switching activity and parasitic capacitances affect power dissipation Low power design for VLSI can be achieved at various levels of the design Research at further levels such as architectural, system, and logic gate levels remains for further study To implement low power design in more advanced technologies such as 90nm, 60nm we need to have appropriate software Nguyễn Thị Đê 94 BIBLIOGRAPHY [1] Adrian Biran & Moshe Breiner (1996), Matlab for Engineers, Addison – Wesley Publishing Company, Great Britain by University Press, Cambridge [2] Brad Peirson (2005), Binary Comparator, Retrieved on May 19, 2010 from http:// www.claymore.engineer.gvsu.edu [3] Cadence Design Systems, Inc (2005), Virtuoso Analog Design Environment, United States of America [4] Cadence Design Systems, Inc (2004), Virtuoso Spectre Circuit Simulator, United States of America [5] Cadence Design Systems, Inc (2004), Virtuoso Layout Editor, United States of America [6] Casey Wallace (2006), Guide to Power Measurement, Retrieved on May 25, 2010 from http:// www.egr.msu.edu [7] David W Parent, A Tutorial Guide for Using CDS Tools for IC Design, Electrical Engineering, SJSU, One Washington Square, San Jose, Retrieved on May 19, 2010 from http://www.engr.sjsu.edu [8] Ekarat Laohavaleeson & Chintan Patel, Virtuoso Layout Editor, Retrieved on May 19, 2010 from http:// www.cs.umbc.edu Nguyễn Thị Đê 95 [9] Jan Rabaey (2009), Low Power Design Essentials, Springer, USA [10] John P Uyemura (2003), CMOS Logic Circuit Design, Kluwer Academic Publishers, United States of America, pp 195 – 196, 206, 224 – 226 [11] Keshab K Parhi (2003, 2004), VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons (Asia) Pte Ltd., Singapore, ISBN 9812-53-023-1 [12] Lee Eng Han, Valerio B Perez, Mark Lambert Cayanes and Mary Grace Salaber (2005), CMOS Transistor Layout KungFu, Retrieved on May 19, 2010 from http:// www.eda-utilities.com [13] Massoud Pedram (1995), Design Technologies for Low Power VLSI, To appear in Encyclopedia of Computer Science and Technology, Department of EE-Systems, University of Southern California, Los Angeles , CA 90089, pp – 2, Retrieved on May 19, 20010 from http://www.citeseerx.ist.psu.edu [14] Neil H E Weste & David Harris (2005), CMOS VLSI Design, Pearson Education Inc., United States of America, pp 186 – 196 [15] Patrick Marchand & O Thomas Holland (2003), Graphic and GUIs with Matlab, Chapman & Hall/ CRC, United States of America [16] Snorre Aunet (2010), “Ultra Low Power / Low Voltage CMOS Circuits”, Proceedings of The first Solid-State Systems Symposium, Vol.1, pp.121 [17] Sung Mo Kang & Yusuf Leblebici (1999), CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill Book Co-Singapore, Singapore, ISBN 0-07292507-8 Nguyễn Thị Đê 96 [18] Wayne Storr (2010), combination/comb_8.html, Retrieved on June 25, 2010 from http://www.electronics-tutorials.ws/ Nguyễn Thị Đê