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Decipes For FPGA
Design Recipes for FPGAs This page intentionally left blank Design Recipes for FPGAs Dr Peter R Wilson AMSTERDAM • BOSTON • HEIDELBERG • LONDON • NEW YORK • OXFORD PARIS • SAN DIEGO • SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO Newnes is an imprint of Elsevier This eBook does not include ancillary media that was packaged with the printed version of the book Newnes is an imprint of Elsevier Linacre House, Jordan Hill, Oxford OX2 8DP 30 Corporate Drive, Suite 400, Burlington MA 01803 First published 2007 Copyright © 2007, Peter R Wilson All rights reserved The right of Peter R Wilson to be identified as the author of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988 No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means electronic, mechanical, photocopying, recording or otherwise without the prior written permission of the publisher Permission may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone (44) (0) 1865 843830; fax (44) (0) 1865 853333; email: permissions@elsevier.com Alternatively you can submit your request online by visiting the Elsevier web site at http://elsevier.com/locate/permissions, and selecting Obtaining permission to use Elsevier material Notice No responsibility is assumed by the publisher for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions or ideas contained in the material herein British Library Cataloguing in Publication Data Wilson, Peter R Design recipes for FPGAs Field programmable gate arrays – Design and construction I Title 621.395 Library of Congress Number: 2007923611 ISBN: 978-0-7506-6845-3 For information on all Newnes publications visit our website at www.books.elsevier.com Printed and bound in Great Britain by MPG Books Ltd, Bodmin Cornwall 07 08 09 10 11 10 Cover image of an Actel RTAX4000S FPGA chip supplied courtesy of Actel – www.actel.com For Heather This page intentionally left blank Contents Acknowledgements xvii Preface xix List of Figures xxi Part Overview Chapter Introduction Why FPGAS? 3 Chapter An FPGA Primer Introduction FPGA evolution Programmable logic devices Field programmable gate arrays FPGA design techniques 10 Design constraints using FPGAs 10 Summary 10 Chapter A VHDL Primer: The Essentials 11 Introduction 11 Entity: model interface 12 Entity definition 12 Ports 13 Generics 13 Constants 14 Entity examples 14 Architecture: model behavior 14 Basic definition of an architecture 14 Architecture declaration section 15 Architecture statement section 15 Process: basic functional unit in VHDL 16 Contents Basic variable types and operators 17 Constants 17 Signals 17 Variables 18 Boolean operators 18 Arithmetic operators 18 Comparison operators 19 Shifting functions 19 Concatenation 19 Decisions and loops 20 If-then-else 20 Case 21 For 21 While and loop 22 Exit 22 Next 22 Hierarchical design 23 Functions 23 Packages 23 Components 24 Procedures 25 Debugging models 26 Assertions 26 Basic data types 26 Basic types 26 Data type: BIT 26 Data type: Boolean 27 Data type: integer 27 Integer subtypes: natural 27 Integer subtypes: positive 27 Data type: character 27 Data type: real 28 Data type: time 28 Summary 28 Chapter Design Automation and Testing for FPGAs 30 Simulation 30 Test benches 30 Test bench goals 30 Simple test bench: instantiating components 31 Adding stimuli 32 Libraries 33 Introduction 33 viii Contents Using libraries 34 Std_logic libraries 35 Std_logic type definition 35 Synthesis 36 Design flow for synthesis 36 Synthesis issues 38 RTL design flow 38 Physical design flow 39 Place and route 40 Recursive cut 40 Timing analysis 40 Design pitfalls 40 VHDL issues for FPGA design 41 Initialization 41 Floating point numbers and operations Summary 41 Part Applications 41 43 Chapter Images and High-Speed Processing 45 Introduction 45 The camera link interface 46 Hardware interface 46 Data rates 47 The Bayer pattern 47 Memory requirements 48 Getting started 49 Specifying the interfaces 51 Defining the top level design 51 System block definitions and interfaces 52 Overall system decomposition 52 Mouse and keyboard interfaces 52 Memory interface 53 The display interface: VGA 53 The cameralink interface 54 The PC interface 55 Summary 56 Chapter Embedded Processors 57 Introduction 57 A simple embedded processor 57 Embedded processor architecture Basic instructions 59 57 ix ...Design Recipes for FPGAs This page intentionally left blank Design Recipes for FPGAs Dr Peter R Wilson AMSTERDAM • BOSTON • HEIDELBERG • LONDON • NEW YORK • OXFORD PARIS • SAN DIEGO •... Introduction Why FPGAS? 3 Chapter An FPGA Primer Introduction FPGA evolution Programmable logic devices Field programmable gate arrays FPGA design techniques 10 Design constraints using FPGAs 10 Summary... Peter R Design recipes for FPGAs Field programmable gate arrays – Design and construction I Title 621.395 Library of Congress Number: 2007923611 ISBN: 978-0-7506-6845-3 For information on all Newnes