136 4 MOS Capacitor ACCUMULATION METAL OXIDE HOLE DENSITY Ec Ei EfP __ _____ 00" 00 E" (a) L-4 fox p-TYPE SILICON tg X INVERSION Ef, Fig. 4.10 Effect of applied voltage on a p-type MOS capacitor; (a) negative voltage V,, = (V, -_ yfb) causes hole accumulation at the surface; (b) positive voltage depletes holes from the silicon surface; and (c) a large positive V,, causes inversion, forming an n-type layer at the silicon surface charged acceptor ions. In other words, a positive charge on the gate induces a negative charge Q, at the silicon surface. Since holes are depleted at the surface it is referred to as the depletion condition. This is analogous to the depletion region in pn junctions discussed in section 2.5. Since hole concentration decreases at the surface, we see from Eq. (4.15) that (Ei - Ef) 4.2 MOS Capacitor at Non-Zero Bias 137 must decrease resulting in Ei coming closer to E, thereby bending the bands downward near the surface (Figure 4.10b). Thus in vg ’ vfb depletion 4s >O, (4.22) Let us now calculate the depletion layer charge. The band bending potential 4(x) must satisfy Poisson’s equation (2.41) and is used to calculate the induced charge Q, within the space charge region of width X, at the surface, also called the depletion width. We refer to this induced charge in the depletion region as the bulk charge denoted by Qb. Applying Gauss’ law we have [cf. Eq. (4.18)] Q, = Q,(depletion) = - E~E,~€,~ (F/cm2). (4.23) Under the depletion approximation (cf. section 2.5.2) n = p = 0 (no free carriers) and the assumption that the substrate is p-type (uniform concentra- tion N, cm- ’) so that No( = Nb) >> N,, the Poisson equation (2.41) becomes I Q, <O. (4.24) Integrating the above equation twice from the interface (x = 0) to the depletion edge (x = X,) and using the boundary conditions 4=4, and -=-&si d4 at x=O (4.25a) dx and d4 dx 4=-=O at x=x, we get (4.2 5 b) (4.26) which gives a relationship between the band bending and the surface potential. The depletion width X, in the above equation can easily be calculated by substituting Eq. (4.26) in (4.24) giving (4.27) 138 4 MOS Capacitor Note that the depletion width given by the equation above is the same as that obtained for one sided step pn junction under the depletion approxima- tion [cf. Eq. (2.53)]. This shows that we can treat the silicon surface/silicon bulk system as a one sided step junction. The depletion or bulk charge Qb can now be obtained from Eq. (4.23) using Eqs. (4.26) and (4.27) giving Q b- - - E 0 E SI .€ SI . = E 0 E sidch1 = - J- (F/cm2). (4.28) Alternatively, Qb can also be obtained by integrating the charge qNb under the depletion width X, giving dx x=o (4.29) where we have made use of Eq. (4.27) for X,. For n-type silicon, Qb, given by Eq. (4.29), is a positive quantity. Note that Eq. (4.27) for X, is in terms of surface potential $s. Since $s itself is a function of gate voltage V, [cf. Eq. (4.20)], one can also write X, in terms of V,. Thus, by substituting $s from Eq. (4.27) and Qs( = Qb) from Eq. (4.29) in Eq. (4.20) and solving the resulting quadratic equation in X, we get, under the depletion approximation :ox \v EOEsiqNb (4.30) Equation (4.30) shows that when V, = Vfb, the depletion width X, = 0, consistent with the definition of the flat band voltage. 4.2.3 Inversion If we continue to increase the positive gate voltage V,,( = V, - V,,), the downward band bending would further increase. In fact, a sufficiently large voltage can cause so much band bending that it may cause the midgap energy Ei to cross over the constant Fermi level E, i.e. E, > Ei. When this happens the surface behaves like n-type material with an electron concentra- tion given by Eq. (2.10a). Note that this n-type surface is formed not by doping but instead by inversion of the original p-type substrate due to the applied gate voltage. This is referred to as the inversion condition and is 4.2 MOS Capacitor at Non-Zero Bias 139 shown in Figure 4.10~. Thus in Vg >> Vfbj inversion 4, >O, (4.3 1) The surface is inverted as soon as E, > Ej. This is called the weak inversion regime because the electron concentration remains small until E, is considerably above Ei. If we further increase Vg,, the concentration of electrons at the surface will equal, and then exceed, the concentration of the holes in the substrate. This is called the strong inversion regime. One may ask, where these electrons (minority carriers) in the p-substrate come from when inversion sets in. Physically speaking these electrons come from the electron-hole generation, within the space charge (depletion) region, caused by the thermal vibration of lattice phonons. The rate of thermal generation depends upon the minority carrier life time zo which is typically in pec (lO-%ec). This means that minority carriers are not immediately available when an inverting gate voltage is applied. The time tin" required to form an inversion layer at the surface is approximated by r Q, <O. c141 (4.32) where ni is the intrinsic carrier concentration. For a typical value of z,, = 1 psec and N, = lOI5 ~m-~, tin" - 0.2 sec. Thus the formation of the inversion layer is a relatively slow process compared to the time required for the holes (majority carriers) topow from or to the silicon surface which is of the order of picoseconds (i.e. the dielectric relaxation time associated with the substrate.) The inversion layer is important from the MOS transistor operation point of view. It is the nature of the inversion layer, that is, number of carriers in the inversion layer (i.e. inversion layer charge Qi), the mobility of the carriers in the layer etc. which determines the current in the transistor. The inversion layer charge Qi can be calculated by including the electron concentration n in Poisson's equation (4.24). Let us first calculate n. Rewriting Eq. (4.4) as ni = N,e-4flvt and substituting ni in Eq. (2.10) we get n = Nbe(@-2#'f)/Vc. (4.33a) and p = N e-6'lvt (4.33b) 140 4 MOS Capacitor At the surface 4 = 4s and therefore, from Eq. (4.33a), the electron concen- tration n, at the surface is given by (4.34) When 4, = 4f, i.e. Ei = E,, we see that n, = ni. That is, the silicon becomes intrinsic. ‘When 4s > g5f, we have E, > Ei and the surface is inverted. At the onset of weak inversion the surface potential 4, is slightly larger than 4f and in this case the depletion width is given by Eq. (4.27). As we further increase 4, by increasing the gate voltage V,, the depletion width X, widens and the electron concentration n, at the surface increases (see Eq. 4.34). When the gate voltage is such that 4,=24,, n,= N,, i.e., the electron concentration at the surface becomes equal to the hole concentration in the bulk. When this happens the surface is said to be strongly inverted, and under this condition, the depletion width reaches its maximum value Xdn,, which can be obtained by replacing $s = 24, in Eq. (4.27). Thus, n sb = N e(4”-24f)/vt. (4.35) The condition 4, = 24, is often referred to as the classical condition for strong inversion. When 4, > 24,, the depletion width increases but very slowly. This is because the inversion charge immediately adjacent to the oxide-silicon interface shields the interior (bulk) of the semiconductor from any additional charge on the gate. - 1.4 ‘5 N~~~=Q~ /q=1~’3cm2 0- N, =to’5cm‘3 T =L*2OK Oo 0 10 20 30 DISTANCE FROM SURFACE,X (A) 0 Fig. 4.11 Calculated electron concentration in silicon (100) and (111) surface as a function of distance from the surface for classical and quantum case. (From Stern and Howard [IS]) 4.2 MOS Capacitor at Non-Zero Bias 141 The thickness of the inversion layer has been calculated using both quantum mechanical and classical approaches. These calculation show [ 15,161 that theo average “inversion layer thickness” at room temperature is about 50 A, depending on the substrate doping concentration and gate voltage. Although not important from a circuit modeling point of view, it is interesting to consider the differences in the charge distributions calculated using the two approaches. The differences are, as shown in Figure 4.11, in two aspects. In the classical case, the electron density has its maximum value at the oxide-silicon interface, and it decreases steadily as we move from the surface into the bulk. In the quantum mechanical case, the electron density is zero at the interface, increases to its maximum value, and then decreases with the distance from the surface. In the classical case, the electron distribution is independent of the crystal orientation while it depends on the crystal orientation in the quantum mechanical case. Figure 4.1 1 also shows that most of the electrons are confined in a layer 50 A thick. For this reason, the motion of the electrons in the channel of a MOSFET can be regarded as two-dimensional, provided device width and length are not very small (cf. section 3.7.7). We will now return to calculate the inversion layer charge density Qi. Including the electron concentration n from Eq. (4.33) in Poisson’s equation (4.24) yields (4.36) Integrating once under the boundary conditions (4.25) we get7 ’ Multiplying both sides of the Poisson’s equation by Z(d+/dx) and using the identity, Eq. (4.36) becomes which can easily be integrated to give (4.37). 142 4 MOS Capacitor Using Gauss’ theorem, we get the induced charge density Q, in the silicon as [cf. Eq. (4.18)] Qs = - EOEsigsi = - Jm ~4, + Ke(4. 24f)/vt1 (C/cm’) (4.38) which could further be simplified to Q, = - JWr4, + ~~e(+s-2~f)/~~1~/~ (C/cm’) (4.39) where we have dropped - 1 after the e4s’vt term because the exponential term is so large in strong inversion that - 1 makes no difference, and in weak inversion the term Vte(4sp24f)ivt is so small that the entire minority carrier term can be neglected. Note that this induce charge Q, is the sum of the inversion charge Qi and depletion charge Qb, that is Qs = Qi + Qb. 21 I I I I I to, = 300 15 -3 Nb = 5x10 cm UI dI II g (4.40) - - 2 3 a: W - n (3 a a 1 V W Qb . - I 1 0.9 0 0 -3 0.4 0.5 0.6 0.7 0.8 SURFACE POTENTIAL, (V) Fig. 4.12 Variation of inversion layer charge density Qi [Eq. (4.41)], bulk charge density Qh [Eq. (4.29)], and the total semiconductor charge density Q,( = Qb + Qi) [Eq. (4.39)] versus surface potential ds in all regimes of device operation for a p-type substrate, N, = 5.1015 cm- ’, to, = 300 A, and V,, = 0 V 4.2 MOS Capacitor at Non-Zero Bias 143 Using Eq. (4.29) for Qb and Eq. (4.39) for Q,, we get the inversion charge Qi from Eq. (4.40) as Qi = - ,/-[,/4, + Vte(4s-2$f)'"t - A] (C/cm2). (4.41) This gives the relationship between the inversion charge density Qi and the surface potential 4,. Figure 4.12 shows various charges as a function of 4,. Note that the depletion charge Qb does not vary appreciably. Also note that Qi and Q, have two distinct regions, which become more apparent when plotted on a logarithmic scale as shown in Figure 4.13a, where Qi is plotted as a function of 4s. These regions are (a) weak inversion and (b) strong inversion. Classically, the condition 4, = 24,. separates the region between the weak and strong inversion. Often, however, the inversion regime is divided into three regions; the third region which lies between the weak and strong inversion is called moderate inversion, defined as the region between 24,. and 24,. + 6Vt (see Figure 4.13b). In this scheme the region beyond 24,. + 67/, is the strong inversion region [IS]. Weak Inversion. Weak inversion sets in when the surface band bending is 4,. and it extends to 24r (see Fig. 4.13). Within this region, the inversion- layer charge Qi is small compared to the depletion-layer charge Qb, that is I Qi I << I Qb I (weak-inversion). (4.42) I 04r 5 Id" > 0.5 0.7 0.9 1.1 SURFACE POTENTIAL, ps(V 1 r 0.5 0.7 0.9 1.1 SURFACE POTENTIAL,$,CV 1 (a) (b) Fig. 4.13 Variation of inversion layer charge density Qi versus surface potential 4s for p-type substrate. (a) showing weak and strong region of operation (b) three different regimes of inversion; weak, moderate and strong inversion. N, = 5.1015 CIT-~, to, = 300A and V,, = OV 144 4 MOS Capacitor For a small 4s, Eq. (4.41) could be simplified* by assuming that the exponential term is small compared to 4s, resulting in the following expression for Qi EE. N Vte(bs- 2bf)/“t (weak-inversion) (C/cm2). (4.43) Thus, in the weak inversion regime Qi is essentially an exponential function of the surface potential 4,. This is plotted as a dashed line in Figure 4.13a. Strong Inversion. Strong inversion is defined by the condition that the inversion layer charge Qi is large compared to the depletion region charge Qb, i.e. 1 Qi I > I Q, I (strong-inversion). (4.44) Here the exponential term in Eq. (4.41) is large compared to 4s and thus Qi in strong inversion becomes Q~ = .J2E,t,iqN,I: e4JZVt (strong-inversion) (C/cmZ)). (4.45) The inversion layer charge is an exponential function of the surface potential with a slope of 1/2V1 (on a log scale). Therefore, a small increment of the surface potential induces a large change in the inversion layer charge. Using Eq. (4.39) for Q, in Eq. (4.20) we get a relationship between the gate voltage and surface potential as This is an implicit relation in +s and must be solved numerically (see Appendix E). The result of such simulations are shown in Figure 4.14. At low gate voltage (> V,.,) 4s increases reasonably rapidly with gate bias and so does the depletion width X, under the gate. This regime corresponds to the depletion and weak inversion regions of the device operation. At larger gate biases, $s hardly changes; 4s has become pinned. The classical condition for the pinning is +,=24, This pinning occurs when strong inversion sets in. The condition when this happens is often called the condition for threshold and the corresponding gate voltage is called thre- shold voltage Vth. It is one of the important device parameter which will be discussed in more details in Chapter 5. Using the Binomial theorem terms we have fi = 1 + x/2 = 1 + x/2 - x2/8 + and retaining the first two 4.2 MOS Capacitor at Non-Zero Bias 145 1.0. , , , I I Ill1 to, = 300 8 N, = i x 10'6~m3 b - - 0.0 IIlI,IIII 0.0 0.L 0.8 1.2 1-6 2.0 GATE VOLTAGE,Vq (V) Fig. 4.14 Variation of surface potential q5s with gate voltage V, obtained using Eq. (4.46). N, = 1.0 x lOI6 cm- ', to, = 300 A, V,, = OV. Cross indicates dS = 24, point which separate weak and strong inversion region To summarize, we have calculated separate expressions for the induced charge Q, that are valid in the depletion [Qb, Eq. (4.29)] and inversion [Qi, Eq. (4.41)] regime of MOS capacitor operation. However, one can easily derive a general expression for Q, that is valid for all the regimes of device operation by including both the holes and electrons and thus solving the Poisson Eq. (2.41). Using Eqs. (4.33) for n and p and noting that in the bulk charge neutrality dictates that N, - N, = npo - ppo, npo and ppo being the carrier density in the bulk (ppo % Nb and npo z Nbe-2'fiVt), the Poisson Eq. (2.41) becomes dx2 E~E,( d2Q, - qNb [I + ,(+-2+f)/Vr - e-4ivt - e-26fivtl for 01 x 5 x,. (4.47) Integrating the above equation, under the boundary condition (4.25), results in the following expression for Q, which includes both holes and electrons 1613 c121, Q, = - J2E,E,iqN,[4, + e-2$fiVt(Vre$JVt - Vr - 4s) + Vre-@J"t - ~~1''~ (C/cm2). (4.48) The charge expression (4.48) is valid in all the regions of MOS capacitor operation-accumulation, depletion, and inversion. It should be pointed out that in the literature Eq. (4.48) is also written in terms of npo and ppo [...]... + e - 2 9 f / V c ( , 9 / v t - I)] + 4s + e-ZOl~/~r(vted~s/vl - 4, v, - vt)1”2 (F/cm2) (4 .57 ) Similarly, the capacitance per unit area C, associated with the interface charge density Qo can be defined as C, dQ = -2 (F/cm2) (4 .58 ) &s so that we have from Eqs (4 .55 )-( 4 .58 ), -dQg - c, + c, (4 .59 ) d4S Combining Eqs (4 .54 ) with (4 .59 ) we get 1 1 c, cox -= - +- 1 c,+co (4.60) Thus the M O S capacitor is... t 'n POLY-Si GATE p-SUBSTRATE -0 .7 0 - DATA MODEL (4.80) Eq (4.69) -1 -5 0 100 200 300 TEMPERATURE,T (K) 400 Fig 4.23 Variation of the flat-band voltage Vfh with temperature for a p-type MOS capacitor Symbols are V f h measured using MOS C-V curve while continuous line is based on Eq (4.80).(After Huang and Gildenblat [ 25] ) Eq (4.911 vfb(T) = @rdT)d ) p 0 1 y ( ~ ) - d)si(T) = 4siare Fermi-potentials... Lett., EDL-10, pp 19 2-1 94 (1989) 1241 P Habas and S Selberherr, ‘On the effect of nodegenerate doping of polysilicon gate modeling , Solid-state Electron., 33, pp in thin oxide MOS devices-analytical 153 9- 154 4 (1990) [ 25] C L Huang and G Sh Gildenblat, ‘MOS flat-band capacitance method at low temperatures’, IEEE Trans Electron Devices, ED-36, pp 143 4-1 439 (1989) [26] R C Jaeger, F H Gaensslen, Simulation. .. 17, pp 73 5- 7 42 (1974) 166 4 MOS Capacitor [19] T W Hickmott and R D Issac, ‘Barrier heights at the polycrystalline Silicon-SiO, interface’, J Appl Phys., 52 , pp 346 4-3 4 75 (1981) [20] G Yaron and D Frohman-Bentchkowsky, ‘Capacitance voltage characterization of poly Si-Si0,-Si structures’, Solid-state Electron., 23, pp 43 3-4 39 (1980) [21] C Y Wong, J Y.-C Sun, Y T Aur, C S Oh, R Angelucci, and B Davari,... Angelucci, and B Davari, ‘Doping of N + and P + poly-Si in a dual-gate CMOS process’, IEEE IEDM, Tech Dig., pp 23 8-2 41 (1988) 1221 R A Chapman, C C Wei, D A Bell, S Aur, G A Brown, and R A Haken, ‘0 .5 micron CMOS for high performance at 3.3V’, IEEE IEDM, Tech Dig., pp 5 2 -5 5 (1988) 1231 C Y Lu, J M Sung, H C Kirsch, S J Hollenius, T E Smith, and L Manchanda, ‘Anomalous C-V characteristics of implanted poly... to use Eq (4.48) for Q , or Eq (4 .57 ) for C, For 4 < 0 we have e - + s >> e C 2 + f > e - 2 + f + 6 sand therefore, E q (4.48) can be approximated as (4.67) 4 MOS Capacitor 152 which on differentiation gives’ (4.68) C,(flat band) = - Combining Eqs (4.68) and (4.61) we get the MOS capacitance at flat band as -1 (flat band) (4.69) Inversion If the gate voltage (V, - V,,) is sufficiently positive such... Electron Devices, ED-27, pp 91 4-9 20 (1980) [27] R R Troutman, ‘Ion-implanted threshold voltage tailoring for insulated gate fieldeffect transistors’, IEEE Trans Electron Devices, ED-24, pp 18 2-1 92 (1977) 1281 A H Marshak and R Shrivastava, ‘On threshold and flat-band voltages for MOS devices with polysilicon gate and nonuniformly doped substrate’, Solid-state Electron., 26, pp 36 1-3 64 (1983) 1291 F... device 168 5 Threshold Voltage n u -* I bl V IC1 Fig 5. 1 (a) Schematic diagram of n-channel MOSFET (nMOST) Its energy band diagram at (b) the source end, and (c) the drain end of the channel Strictly speaking, modeling a MOSFET is a three-dimensional (3-D) problem; however, for all practical purposes (unless the width Wand length L are very small) we can treat the system as a 2-D problem in the x and y... from Ideal C-V Curves 157 u" V z a t- I I vf b -Vg -GATE 0 VOLTAGE I V ) - - C +Vg Fig 4.19 Influence of the metal-semiconductor work function difference Qms and fixed oxide charge Q, on H F C-V curve for an MOS capacitor Curve A is for ideal case with Qms = 0 and Q, = 0, while curve B is experimental curve Parallel shift of curve A to curve B is direct measure of V,, charges (Qo = 0) and Oms 0, so... However, for n-type substrate with donor-like traps C-V curve will show smallest shift in accumulation The shift continues to increase as the device goes through flat band, depletion and inversion 4 .5 Anomalous C-V Curve I59 cox INTERFACE TRAPS (DONOR LIKE) -Vg +GATE 0 VOLTAGE ( V ) - +Vg Fig 4.20 Influence of the interface traps on the high frequency MOS C-V curve Curve A 0 ,I ^ _.,^ : 1 * * , .- :- . &s C, = -2 (F/cm2) so that we have from Eqs. (4 .55 )-( 4 .58 ), dQg - c, + c,. d4S Combining Eqs. (4 .54 ) with (4 .59 ) we get 11 1 + -= - c, cox c,+co (4 .58 ) (4 .59 ) (4.60). (4 .56 ) and, can easily be obtained by differentiating Eq. (4.48) giving the follow- ing expression for C, mEOEsi [1 - e-4./vt + e-29f/Vc(,9./vt - I)] 2[l/,e-9s/vr + 4s - v,. operation for a p-type substrate, N, = 5. 10 15 cm- ’, to, = 300 A, and V,, = 0 V 4.2 MOS Capacitor at Non-Zero Bias 143 Using Eq. (4.29) for Qb and Eq. (4.39) for Q,,