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VHDL Programming by Example 4th Edition
VHDL:Programmingby ExampleDouglas L. PerryFourth EditionMcGraw-HillNew York •Chicago •San Francisco •Lisbon •LondonMadrid •Mexico City •Milan •New Delhi •San Juan Seoul •Singapore •Sydney •Toronto Copyright © 2002 by The McGraw-Hill Companies, Inc. All rights reserved. Manufactured in the United States of America. Except aspermitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form orby any means, or stored in a database or retrieval system, without the prior written permission of the publisher. 0-07-140070-2 All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trade-marked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringe-ment of the trademark. Where such designations appear in this book, they have been printed with initial caps. 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CONTENTSForeword xiiiPreface xvAcknowledgments xviiiChapter 1 Introduction to VHDL 1VHDL Terms 2Describing Hardware in VHDL 3Entity 3Architectures 4Concurrent Signal Assignment 5Event Scheduling 6Statement Concurrency 6Structural Designs 7Sequential Behavior 8Process Statements 9Process Declarative Region 9Process Statement Part 9Process Execution 10Sequential Statements 10Architecture Selection 11Configuration Statements 11Power of Configurations 12Chapter 2 Behavioral Modeling 15Introduction to Behavioral Modeling 16Transport Versus Inertial Delay 20Inertial Delay 20Transport Delay 21Inertial Delay Model 22Transport Delay Model 23Simulation Deltas 23Drivers 27Driver Creation 27Bad Multiple Driver Model 28Generics 29Block Statements 31Guarded Blocks 35 Chapter 3 Sequential Processing 39Process Statement 40Sensitivity List 40Process Example 40Signal Assignment Versus Variable Assignment 42Incorrect Mux Example 43Correct Mux Example 45Sequential Statements 46IF Statements 47CASE Statements 48LOOP Statements 50NEXT Statement 53EXIT Statement 54ASSERT Statement 56Assertion BNF 57WAIT Statements 59WAIT ON Signal 62WAIT UNTIL Expression 62WAIT FOR time_expression 62Multiple WAIT Conditions 63WAIT Time-Out 64Sensitivity List Versus WAIT Statement 66Concurrent Assignment Problem 67Passive Processes 70Chapter 4 Data Types 73Object Types 74Signal 74Variables 76Constants 77Data Types 78Scalar Types 79Composite Types 86Incomplete Types 98File Types 102File Type Caveats 105Subtypes 105Chapter 5 Subprograms and Packages 109Subprograms 110Function 110Contentsvi Conversion Functions 113Resolution Functions 119Procedures 133Packages 135Package Declaration 136Deferred Constants 136Subprogram Declaration 137Package Body 138Chapter 6 Predefined Attributes 143Value Kind Attributes 144Value Type Attributes 144Value Array Attributes 147Value Block Attributes 149Function Kind Attributes 151Function Type Attributes 151Function Array Attributes 154Function Signal Attributes 156Attributes ’EVENT and ’LAST_VALUE 157Attribute ’LAST_EVENT 158Attribute ’ACTIVE and ’LAST_ACTIVE 160Signal Kind Attributes 160Attribute ’DELAYED 161Attribute ’STABLE 164Attribute ’QUIET 166Attribute ’TRANSACTION 168Type Kind Attributes 169Range Kind Attributes 170Chapter 7 Configurations 173Default Configurations 174Component Configurations 176Lower-Level Configurations 179Entity-Architecture Pair Configuration 180Port Maps 181Mapping Library Entities 183Generics in Configurations 185Generic Value Specification in Architecture 188Generic Specifications in Configurations 190Board-Socket-Chip Analogy 195Block Configurations 199Architecture Configurations 201viiContents Chapter 8 Advanced Topics 205Overloading 206Subprogram Overloading 206Overloading Operators 210Aliases 215Qualified Expressions 215User-Defined Attributes 218Generate Statements 220Irregular Generate Statement 222TextIO 224Chapter 9 Synthesis 231Register Transfer Level Description 232Constraints 237Timing Constraints 238Clock Constraints 238Attributes 239Load 240Drive 240Arrival Time 240Technology Libraries 241Synthesis 243Translation 243Boolean Optimization 244Flattening 245Factoring 246Mapping to Gates 247Chapter 10 VHDL Synthesis 251Simple Gate — Concurrent Assignment 252IF Control Flow Statements 253Case Control Flow Statements 256Simple Sequential Statements 257Asynchronous Reset 259Asynchronous Preset and Clear 261More Complex Sequential Statements 262Four-Bit Shifter 264State Machine Example 266Contentsviii Chapter 11 High Level Design Flow 273RTL Simulation 275VHDL Synthesis 277Functional Gate-Level Verification 283Place and Route 284Post Layout Timing Simulation 286Static Timing 287Chapter 12 Top-Level System Design 289CPU Design 290Top-Level System Operation 290Instructions 291Sample Instruction Representation 292CPU Top-Level Design 293Block Copy Operation 299Chapter 13 CPU: Synthesis Description 303ALU 306Comp 309Control 311Reg 321Regarray 322Shift 324Trireg 326Chapter 14 CPU: RTL Simulation 329Testbenches 330Kinds of Testbenches 331Stimulus Only 333Full Testbench 337Simulator Specific 340Hybrid Testbenches 342Fast Testbench 345CPU Simulation 349Chapter 15 CPU Design: Synthesis Results 357ixContents [...]... to write good VHDL design descriptions. The goal is to provide enough VHDL and design methodology information to enable a designer to quickly write good VHDL designs and be able to verify the results. It will also attempt to bring the designer with little or no knowledge of VHDL, to the level of writing complex VHDL descriptions. It is not intended to show every pos- sible construct of VHDL in every... of types available for use in VHDL. Examples are given for each of the types showing how they would be used in a real example. In Chapter 5 the concepts of subprograms and packages are introduced. The different uses for functions are given, as well as the features available in VHDL packages. Chapter 6 introduces the five kinds of VHDL attributes. Each attribute kind has examples describing how to use... advantage. Examples are given which describe the pur- pose of each of the attributes. Chapters 7 and 8 will introduce some of the more advanced VHDL features to the reader. Chapter 7 discusses how VHDL configurations can be used to construct and manage complex VHDL designs. Each of the different configuration styles are discussed along with examples showing usage. Chapter 8 introduces more of the VHDL advanced... 31 Guarded Blocks 35 3 Introduction to VHDL ■ Bus. The term “bus” usually brings to mind a group of signals or a particular method of communication used in the design of hard- ware. In VHDL, a bus is a special kind of signal that may have its drivers turned off. ■ Attribute. An attribute is data that are attached to VHDL objects or predefined data about VHDL objects. Examples are the current drive capability... found in the VHDL Language Reference Manual. I can only hope that you the reader will have as much fun read- ing this book and working with VHDL as I did in writing it. xvii Preface FOREWORD VHDL has been at the heart of electronic design productivity since ini- tial ratification by the IEEE in 1987. For almost 15 years the electronic design automation industry has expanded the use of VHDL from initial concept... efficient, and correct VHDL descriptions of hardware designs. This book is organized into three logical sections. The first section of the book will introduce the VHDL language, the second section walks through a VHDL based design process including simulation, synthesis, place and route, and VITAL simulation; and the third section walks through a design example of a small CPU design from VHDL capture to... about the language and examples used throughout the book. In the first section VHDL features are introduced one or more at a time. As each feature is introduced, one or more real examples are given to show how the feature would be used. The first section consists of Chapters 1 through 8, and each chapter introduces a basic description capability of VHDL. Chapter 1 discusses how VHDL design relates to... facilitated by industry backing in a consortium of systems, electronic design automation and semiconductor companies now known as Accellera. And when the ASIC industry needed a standard way to convey gate- level design data and timing information in VHDL, one of Accellera’s progenitors (VHDL International) sponsored the IEEE VHDL team to build a companion standard. The IEEE 1076.4 VITAL (VHDL Initiative Towards... have seen, generics have many uses. The uses of generics are limited only by the creativity of the model writer. Block Statements Blocks are a partitioning mechanism within VHDL that allow the designer CONTENTS Foreword xiii Preface xv Acknowledgments xviii Chapter 1 Introduction to VHDL 1 VHDL Terms 2 Describing Hardware in VHDL 3 Entity 3 Architectures 4 Concurrent Signal Assignment 5 Event Scheduling... can help speed verification. Finally there are three appendices at the end of the book to provide ref- erence information. Appendix A is a listing of the IEEE 1164 STD_LOGIC VHDL: Programming by Example Douglas L. Perry Fourth Edition McGraw-Hill New York • Chicago • San Francisco • Lisbon • London Madrid • Mexico City • Milan • New Delhi • San Juan Seoul • Singapore • Sydney • Toronto . VHDL: Programmingby ExampleDouglas L. PerryFourth EditionMcGraw-HillNew York •Chicago •San Francisco. ’80s by the U.S. Departmentof Defense. Its roots are in the ADA language, as will beseen by the overall structure of VHDL as well as otherVHDL statements.VHDL