RANDOM PATTERN EFFECTIVENESS 467 Figure 9.9 Enhancing random test. 9.4.3 Weighted Random Patterns Another approach to testing random pattern-resistant faults makes use of weighted random patterns (WRP). Sensitizing and propagating faults often require that some primary inputs have a disproportionate number of 1s or 0s. One approach developed for sequential circuits determines the frequency with which inputs are required to change. This is done by simulating the circuit and measuring switching activity at the internal nodes as signal changes occur on the individual primary inputs. Inputs that generate the highest amount of internal activity are deemed most important and are assigned higher weights than others that induce less internal activity. 13 Those with the highest weights are then required to switch more often. A test circuit was designed to allocate signal changes based on the weights assigned during simulation. This hardware scheme is illustrated in Figure 9.10. An LFSR generates n-bit patterns. These patterns drive a 1 of 2 n selector or decoder. A subset j k of the outputs from the selector drive bit-changer k which in turn drives input k of the IC, where , and m is the number of inputs to the IC. The number j k is proportional to the weight assigned to input k. The bit-changers are designed so that only one of them changes in response to a change on the selector outputs; hence only one primary input changes at the IC on any vector. When gener- ating weights for the inputs, special consideration is given to reset and clock inputs to the circuit. Figure 9.10 Weighted pattern generator. (a) (b) j k k 1= m ∑ 2 n ≤ n L F S R S e l e c t o r Bit changer Bit changer Bit changer Input 1 Input 2 Input m 468 BUILT-IN SELF-TEST The WRP is also useful for combinational circuits where BIST is employed. Con- sider, for example, a circuit made up of a single 12-input AND gate. It has 4096 pos- sible input combinations. Of these, only one, the all-1s combination, will detect a stuck-at-0 at the output. To detect a stuck-at-1 on any input requires a 0 on that input and 1s on all of the remaining 11 inputs. If this circuit were being tested with an LFSR, it would take, on average, 2048 patterns before the all-1s combination would appear, enabling detection of a stuck-at-0 at the output. In general, this circuit needs a high percentage of 1s on its inputs in order to detect any of the faults. The OR gate is even more troublesome since an all-0s pattern is needed to test for a stuck-at-1 fault on the output, and the LFSR normally does not generate the all-0s pattern. To employ WRPs on a combinational circuit, it is first necessary to determine how to bias each circuit input to a 1 or a 0. The calculation of WRP values is based on increasing the probability of occurrence of the nonblocking or noncontrolling value (NCV) at the inputs to a gate. 14 For the AND gate mentioned previously, it is desirable to increase the probability of applying 1s to each of its inputs. For an OR gate, the objective is to increase the probability of applying 0s to its inputs. The weighting algorithm must also improve the probability of propagating error signals through the gate. The first step in computing biasing values is to determine the number of device inputs (NDI) controlling each gate in the circuit. This is the number of primary inputs and flip-flops contained in the cone of that gate. This value, denoted as NDI g , is divided by NDI i , the NDI for each input to that gate. That gives the ratio R i of the NCV to the controlling value for each gate. This is illustrated in Figure 9.11, where the total number of inputs to gate D, NDI D , is 9. NDI A is 4; hence the ratio R i of NDI D to NDI A is 9 to 4. Two additional numbers, W0 and W1, the 0 weight and the 1 weight, must be computed for each gate in the circuit. Initially, these two values are set to 1. The algorithm for computing the weights at the inputs to the circuit proceeds as follows: 1. Determine the NDI g for all logic gates in the circuit. 2. Assign numbers W0 and W1 to each gate; initially assign them both to 1. Figure 9.11 Calculating bias numbers. 9:2 9:4 9:3 A B C D I 9 I 2 I 2 I 1 I 8 I 7 I 6 I 5 I 4 PO RANDOM PATTERN EFFECTIVENESS 469 3. Backtrace from each output. When backtracing from a gate g to an input gate i, adjust the weights W0 and W1 of gate i according to Table 9.1. When a gate occurs in two or more cones, the value of W0 or W1 is the larger of the exist- ing value and the newly calculated value. 4. Determine the weighted value WV. It represents the logic value to which the input is to be biased. If W0 > W1, then WV = 0, else WV = 1. 5. Determine the weighting factor WF. It represents the amount of biasing toward the weighted value. If WV = 0, then WF = W0/W1, else WF = W1/W0. Example Consider the circuit in Figure 9.11. Initially, all the gates are assigned weights W0 = W1 = 1. Then the backtrace begins. Table 9.2 tabulates the results. When backtracing from gate D to gate A, Table 9.1 states that if gate g is an OR gate, then W0 i = (R i ⋅ W0 g ) and W1 i = W1 g for gate i. In this example, gate g is the OR gate labeled D and W0 g = W1 g = 1. Also, R i = 9/4. Thus, W0 i = 9/4, or 2.25. In the next step of the backtrace, g refers to gate A, an AND gate, and i refers to primary inputs I 1 to I 4 . Also, R i = 4/1 = 4. The entry for the AND gate in Table 9.1 states that W0 i = W0 g and W1 i = (R i ⋅ WI g ). So the weights for I 1 to I 4 are W0 i = 2.25 and W1 i = 4. The remaining calculations are carried out in similar fashion. From the results it is seen that inputs I 1 to I 4 must be biased to a 1 with a weighting factor WF = 4/2.25 = 1.77. Inputs I 5 and I 6 are biased to a 0 with WF = 4.5/2 = 2.25. Finally, inputs I 7 to I 9 have identical 0 and 1 weights, so biasing is not required for those inputs. TABLE 9.1 Weighting Formulas Logic Function W0 i W1 i AND W0 g R i .W1 g NAND W1 g R i .W0 g OR R i .W0 g W1 g NOR R i .W1 g W0 g TABLE 9.2 Tabulating Weights From (g) To (i) W0 i W1 i PO gate D 11 gate D gate A 2.25 1 gate A I 1 −I 4 2.25 4 gate D gate B 4.5 1 gate B I 5 −I 6 4.5 2 gate D gate C 31 gate C I 7 −I 9 33  470 BUILT-IN SELF-TEST The calculation of weights for a circuit of any significant size will invariably lead to fractions that are not realistic to implement. The weights should, therefore, be used as guidelines. For example, if a weight is calculated to be 3.823, it is sufficient to use an integer weighting factor of 4. The weighted inputs can be generated by selecting multiple bits from the LFSR and performing logic operations on them. An LFSR corresponding to a primitive polynomial will generate, for all practical pur- poses, an equal number of 1s and 0s (the all-0s combination is not generated). So, if a ratio 3:1 of 1s to 0s is desired, then an OR gate can be used to OR together two bits of the LFSR with the expectation that, on average, one out of every four vectors will have 0s in both positions. Similarly, for a ratio 3:1 of 0s to 1s the output of the OR can be inverted, or an AND gate can be used. ANDing/ORing three or four LFSR bits results in ratios of 7:1 and 15:1. More complex logic operations on the LFSR bits can provide other ratios. When backtracing from two or more outputs, there is a possibility that an input may have to be biased so as to favor a logic 0 when backtracing from one output and it may be required to favor a logic 1 when backtracing from another output. How this situation is handled will ultimately depend on the method of test. If test patterns are being applied by a tester that is capable of biasing pseudo-random patterns, then it might be reasonable to use one set of weights for part of the test, then switch to an alternate set of weights. However, if the test environment is complete BIST, a com- promise might require taking some average of the weights calculated during the backtraces. Another possible approach is to consider the number of inputs in each cone, giving preference to the cone with a larger number of inputs since the smaller cone may have a larger percentage of its complete set of input patterns applied. Previously it had been mentioned that one approach to determining the weights on the inputs could be accomplished by switching individual inputs one at a time and measuring the internal activity in the circuit using a logic simulator. Another approach that has been proposed involves using ATPG and a fault simulator to ini- tially achieve high-fault coverage. 15 Use these test vectors to determine the fre- quency of occurrence of 1s and 0s on the inputs. The frequency of occurrence helps to determine the weighting factors for the individual circuit inputs. It would seem odd to take this approach since one of the reasons for adopting BIST is to avoid the use of ATPG and fault simulation, but the approach does reduce or eliminate the reli- ance on a potentially expensive tester. 9.4.4 Aliasing Up to this point the discussion has centered around how to improve fault coverage of BIST while minimizing the number of applied vectors. An intrinsic problem that has received considerable attention is a condition referred to as aliasing. If a fault is sen- sitized by applied stimuli, with the result that an error signal reaches an LFSR or MISR, the resulting signature generated by the error signal will map into one of 2 n possible signatures, where n is the number of stages in the LFSR or MISR. It is pos- sible for the error signature to map into the same signature as the fault-free device. With 2 16 signatures, the probability that the error signal generated by the fault will SELF-TEST APPLICATIONS 471 be masked by aliasing is 1 out of 2 16 , or about 0.0015%. If a functional register is being used to generate signatures and if it has a small number of stages, thus intro- ducing an unacceptably high aliasing error, the functional register can be extended by adding additional stages that are used strictly for the purpose of generating a sig- nature with more bit positions, in order to reduce the aliasing error. 9.4.5 Some BIST Results The object of BIST is to apply sufficient patterns to obtain acceptable fault coverage, recognizing that a complete exhaustive test is impractical, and that there will be faults that escape detection. The data in Table 9.3 shows the improvement in fault simulation, as the number of random test vectors applied to two circuits increases from 100 to 10,000. 16 For the sake of comparison, fault coverage obtained with an ATPG is also listed. The numbers of test patterns generated by the ATPG are not given, but another ATPG under similar conditions (i.e., combinational logic tested via scan path) generated 61 to 198 test vectors and obtained fault coverage ranging between 99.1% and 100% when applied to circuit partitions with gate counts ranging from 2900 to 9400 gates. 17 9.5 SELF-TEST APPLICATIONS This section contains examples illustrating some of the ways in which LFSRs have been used to advantage in self-test applications. The nature of the LFSR is such that it lends itself to many different configurations and can be applied to many diverse applications. Here we will see applications ranging from large circuits with a total commitment to BIST, to a small, 8-bit microprocessor that uses an ad hoc form of BIST. 9.5.1 Microprocessor-Based Signature Analysis It must be pointed out here that BIST, using random patterns, is subject to con- straints imposed by the design environment. For example, when testing off-the-shelf products such as microprocessors, characterized by a great deal of complex control logic, internal operations can be difficult to control if no mechanism is provided for that purpose. Once set in operation by an op-code, the logic may run for many clock TABLE 9.3 Fault Coverage with Random Patterns Number of Gates No. Random Patterns Fault percentage with ATPG 100 1000 10,000 Chip1 926 86.1 94.1 96.3 96.6 Chip2 1103 75.2 92.3 95.9 97.1 472 BUILT-IN SELF-TEST cycles independent of external stimuli. Nevertheless, as illustrated in this section, it is possible to use BIST effectively to test and diagnose defects in systems using off- the-shelf components. Hewlett-Packard used signature analysis to test microprocessor-based boards. 18 The test stimuli consisted of both exhaustive functional patterns and specific, fault- oriented test patterns. With either type of pattern, output responses are compressed into four-digit hexadecimal signatures. The signature generator compacts the response data generated during testing of the system. The basic configuration is illustrated in Figure 9.12. It is a rather typical micro- processor configuration; a number of devices are joined together by address and data buses and controlled by the microprocessor. Included are two items not usually seen on such diagrams: a free-run control and a bus jumper. When in the test mode, the bus jumper isolates the microprocessor from all other devices on the bus. In response to a test signal or system reset, the free-run control forces an instruction such as an NOP (no operation) onto the microprocessor data input. This instruction performs no operation, it simply causes the program counter to increment through its address range. Since no other instruction can reach the microprocessor inputs while the bus jumper is removed, it will continue to increment the program counter at each clock cycle and put the incremented address onto the address bus. The microprocessor might generate 64K addresses or more, depending on the number of address bits. To evaluate each bit in a stream of 64K bits, for each of 16 address lines, requires stor- ing a million bits of data and comparing these individually with the response at the microprocessor address output. To avoid this data storage problem, each bit stream is compressed into a 16-bit signature. For 16 address lines, a total of 256 data bits must be stored. The Hewlett-Packard implementation used the LFSR illustrated in Figure 9.2. Because testability features are designed into the product, the tests can be run at the product’s native clock speed, while the LFSR monitors the data bus and accumulates a signature. After the program counter has been verified, the ROM can be tested by running through its entire address space and generating a signature on each of its output pins. Figure 9.12 Microprocessor-based signature analysis. Microprocessor Bus jumper Free run control ROM RAM Peripherals Control Data bus Address bus SELF-TEST APPLICATIONS 473 The ROM, like the program counter, is run through its address space by putting the board in the free run mode and generating the NOP instruction. After the ROM has been checked, the bus jumper is replaced and a diagnostic program in ROM can be run to exercise the microprocessor and other remaining circuits on the board. Note that diagnostic tests can reside in the ROM that contains the operating system and other functional code, or that ROM can be removed and replaced by another ROM that contains only test sequences. When the microprocessor is in control, it can exer- cise the RAM using any of a number of standard memory tests. Test stimuli for the peripherals are device-specific and could in fact be developed using a pseudo- random generator. The signature analyzer used to create signatures has several inputs, including START, STOP, CLOCK, and DATA. The DATA input is connected to a signal point that is to be monitored in the logic board being tested. The START and STOP sig- nals define a window in time during which DATA input is to be sampled while the CLOCK determines when the sampling process occurs. All three of these signals are derived from the board under test and can be set to trigger on either the rising or fall- ing edge of the signal. The START signal may come from a system reset signal or it may be obtained by decoding some combination on the address lines, or a special bit in the instruction ROM can be dedicated to providing the signal. The STOP signal that terminates the sampling process is likewise derived from a signal in the logic circuit being tested. The CLOCK is usually obtained from the system clock of the board being tested. For a signature to be useful, it is necessary to know what signature is expected. Therefore, documentation must be provided listing the signatures expected at the IC pins being probed. The documentation may be a diagram of the circuit with the sig- natures imprinted adjacent to the circuit nodes, much like the oscilloscope wave- forms found on television schematics, or it can be presented in tabular form, where the table contains a list of ICs and pin numbers with the signature expected at each signal pin for which a meaningful signature exists. This is illustrated for a hypothet- ical circuit in Table 9.4. TABLE 9.4 Signature Table IC Pin Signature IC Pin Signature U21 2 8UP3 U41 3 37A3 3 713A 5 84U4 4 01F6 6 F0P1 7 69CH 8 1147 9 8P7U 9 77H1 11 684C 11 10UP 15 H1C3 14 1359 15 U11A 474 BUILT-IN SELF-TEST During test the DATA probe of the signature analyzer is moved from node to node. At each node the test is rerun in its entirety and the signature registered by the signature analyzer is checked against the value listed in the table. This operation is analogous to the guided probe used on automatic test equipment (cf. Section 6.9.3). It traces through a circuit until a device is found that generates an incorrect output signature but which is driven by devices that all produce correct signatures on their outputs. Note that the letters comprising the signature are not the expected 0–9 and A–F. The numerical digits are retained but the letters A–F have been replaced by ACFHPU, in that order, for purposes of readability and compatibility with seven- segment displays. 19 A motive for inserting stimulus generation within the circuits to be tested, and compaction of the output response, is to make field repair of logic boards possible. This in turn can help to reduce investment in inventory of logic boards. It has been estimated that a manufacturer of logic boards may have up to 5% of its assets tied up in replacement board kits and “floaters”—that is, boards in transit between customer sites and a repair depot. Worse still, repair centers report no problems found in up to 50% of some types of returned boards. 20 A good test, one that can be applied suc- cessfully to help diagnose and repair logic boards in the field, even if only part of the time, can significantly reduce inventory and minimize the drain on a company’s resources. The use of signature analysis does not obviate the need for sound design prac- tices. Signature analysis is useful only if the bit streams at various nodes are repeat- able. If even a single bit is susceptible to races, hazards, uninitialized flip-flops, or disturbances from asynchronous inputs such as interrupts, then false signatures will occur with the result that confidence in the signature diminishes or, worse still, cor- rectly operating components are replaced. Needlessly replacing nonfaulted devices in a microprocessor environment can negate the advantages provided by signature analysis. 9.5.2 Self-Test Using MISR/Parallel SRSG (STUMPS) STUMPS was the outcome of a research effort conducted at IBM Corp. in the early 1980s for the purpose of developing a methodology to test multichip logic mod- ules. 21 The multichip logic module (MLM) is a carrier that holds many chips. The SRSG (shift register sequence generator) is their terminology for what is referred to here as a PRG. Development of STUMPS was preceded by a study of several configurations to identify their advantages and disadvantages. The configuration depicted in Figure 9.13, referred to as a random test socket (RTS), was one of those studied. The PRG generates stimuli that are scanned into the MLM at the SRI (shift register input) pin. The bits are scanned out at the SRO (shift register output) and are clocked into a TRC to generate a signature. The scan elements are made up of LSSD SRLs (shift register latches). Primary inputs are also stimulated by a PRG, and primary outputs are sampled by a MISR. This activity is under control of a test controller that determines how many clock cycles are needed to load the internal scan chains. The SELF-TEST APPLICATIONS 475 Figure 9.13 Random test socket. test controller also controls the multichip clocks (MCs). When the test is done, the test controller compares the signatures in the MISR’s to the expected signatures to determine if the correct response was obtained. One drawback to the random test socket is the duration of the test. The assump- tions are: All of the SRLs are connected into a single scan path. There would be about 10,000 SRLs in a typical scan chain. The clock period is 50 ns. About one million random vectors would be applied. A new vector is loaded while the previous response is clocked into the MISR. With these assumptions, the test time for an MLM is about 8 minutes, which was deemed excessive. A second configuration, called simultaneous self-test (SST), converts every SRL into a self-test SRL, as shown in Figure 9.14(a). At each clock, data from the combi- national logic is XOR’ed with data from a previous scan element, as shown in Figure 9.14(b). This was determined to produce reasonably random stimuli. Since every clock resulted in a new test, the application of test stimuli could be accom- plished very quickly. The drawbacks to this approach were the requirement for a test mode I/O pin and the need for a special device, such as a test socket, to handle test- ing of the primary inputs and outputs. A third configuration that was analyzed was STUMPS. The scan path in each chip is driven by an output of the PRG (recall from the discussion of LFSRs that a pseudo-random bit stream can be obtained from each SRL in the LFSR). The scan- out pin of each chip drives an input to the MISR. This is illustrated in Figure 9.15, where each chain from PRG to MISR corresponds to a one chip. The number of clocks applied to the circuit is determined by the longest scan length. The chips with shorter scan lengths will have extra bits clocked through them, but there is no pen- alty for that. The logic from the primary outputs of each chip drive the primary inputs to other chips on the MLM. Only the primary inputs and outputs of the MLM have to be dealt with individually from the rest of the test configuration. Multichip logic module PRG M ISR PRG TRC Test controller PO’sPI’s } A B SRI SRO } MCs 476 BUILT-IN SELF-TEST Figure 9.14 Simultaneous self-test. Unlike RTS, which connects the scan paths of all the individual chips into one long scan path, scan paths for individual chips in STUMPS are directly connected to the PRG and the MISR, using the LSSD scan-in and scan-out pins, so loading stim- uli and unloading response can be accomplished more quickly, although not as quickly as with SST. An advantage of STUMPS is the fact that, apart from the PRG and MISR, it is essentially an LSSD configuration. Since a commitment to LSSD has already been made and since STUMPS does not require any I/O pins in addition to those committed to LSSD, there is no additional I/O penalty for the use of STUMPS. The PRG and MISR employed in STUMPS are contained in a separate test chip, and each MLM contains one or more test chips to control the test process. A MLM that contained 100 chips would require two test chips. Since the test chips are about the same size as the functional chips, they represented about a 2% overhead for STUMPS. The circuit in Figure 9.16 illustrates how the test chip generates the pseudo-random sequences and the signatures. Figure 9.15 STUMPS architecture. Data C Scan-in Shift A Shift B L1 L2 Test Mode SRL + SRL Data Scan-in Scan-out Scan-out (a) (b) + + Scan-in MISR PRG SI 1 SI 2 SI 3 SI n SO 1 SO 2 SO 3 SO N Comb. logic Comb. logic [...]... the testing of circuits where, for various reasons, there is no visibility into the internal structure of the device or system All testing is performed based on an understanding of the functionality of the device Because of this lack of visibility, the methods described here are often referred to as black-box testing Testing of microprocessors and other complex logic devices can be aided by ordering and/ or... partial order ≥ is defined such that If B ⋅ ρ1 ⋅ a and B ⋅ ρ2 ⋅ b, then B ≥ a ⋅ b In words, a test of B must follow the test of a AND b In effect, if B is controlled through a and observed through b, then a and b must both be tested before B is tested However, it may be that two devices C and D have the property that C ≥ D and D ≥ C In that case A ≡ B and A and B are said to be indistinguishable This would... output is active In fact, since it is both self -testing and fault-secure, it is said to be totally self-checking.44 3 -8 MUX Figure 9. 28 Self -testing decoder Error FAULT TOLERANCE 499 The multiplexer can be designed with self -testing features that take advantage of the function The multiplexer must produce a logic 1(0) on its output if all data inputs are at logic 1(0), regardless of which input port was... devices such as counters and ALUs (arithmetic, logic unit) may be included in the graph It must be recognized that these devices require more than simply passing data through them (cf Section 7 .8, Behavioral Fault Modeling) 9 .8 FAULT TOLERANCE If we distinguish between the logic machine, which is an abstract specification defining tasks to be performed and algorithms to perform them, and the host, which is... the random combinational logic, known as LBIST (logic BIST), another BIST function is performed by ABIST (array BIST), which provides atspeed testing of the embedded arrays An ABIST controller can be shared among several arrays This both reduces the test overhead per array and permits reduced test times, since arrays can be tested in parallel The STUMPS logic tests are supplemented by weighted random... aforementioned three tests are applied and there is a high degree of confidence that the test circuits are working properly, the logic test mode is entered STUMPS applies stimuli to the combinational logic on the module and creates a signature at the MISR The tests are under control of a tester when testing individual modules The tester applies stimuli to the primary inputs and generates signatures at the... input control signals and one output signal Three other signals are available to handle error signals when the chip is used functionally The chip select (CS) makes it possible to access a single chip within a system Control (CON) is used to differentiate between commands and data Transfer (TR) indicates that valid data are available and Loop-in is used to serially shift in commands or data Loop-out... decremented, or it can be used to receive the results of arithmetic and logic operations, and in the process the condition codes (CC) are updated The individual arcs are numbered for convenience in referring to them If we denote an I/O port used for input as IN and denote an I/O port used for output as OUT, and if we assign graph nodes to IN and OUT, then a directed arc exists from IN to Reg (from Reg to... comprised of many hundreds of thousands of logic gates It might have different names and somewhat different assignments in different systems, but one thing the test controllers had in common was the responsibility to respond to error symptoms and help diagnose faults more quickly Test controllers used some or all of the methods discussed in this and previous chapters, and they used some methods that will... more sophisticated analysis tools such as the hard drive reliability standard called Self-Monitoring, Analysis and Reporting Technology (SMART) This standard provides for on-drive sensing hardware for reporting drive status and software to collect and intrepret that data The object is to measure physical degradation in the drive and alert the user to imminent failures These measurements are recorded . RANDOM PATTERN EFFECTIVENESS 467 Figure 9.9 Enhancing random test. 9.4.3 Weighted Random Patterns Another approach to testing random pattern-resistant faults makes use of weighted random. 9.4 Signature Table IC Pin Signature IC Pin Signature U21 2 8UP3 U41 3 37A3 3 713A 5 84 U4 4 01F6 6 F0P1 7 69CH 8 1147 9 8P7U 9 77H1 11 684 C 11 10UP 15 H1C3 14 1359 15 U11A 474 BUILT-IN SELF-TEST During. commands and data. Transfer (TR) indicates that valid data are available and Loop-in is used to serially shift in commands or data. Loop-out is a single output signal. SELF-TEST APPLICATIONS 481 Figure