1-20 Memory, Microprocessor, and ASIC signal C i and C f to the flip-flops R i and R f are denoted by and , respectively. The input and output data signals to R i and R f are denoted by Di, Qi , Df and Q f , respectively. An analysis of the timing properties of the local data path shown in Fig. 1.14 is offered in the following sections. First, the timing relationships to prevent the late arrival of data signals to R f are examined in the next subsection. The timing relationships to prevent the early arrival of signals to the register R f are then described, followed by analyses that borrow some notation from Refs. 11 and 12. Similar analyses of synchronous circuits from the timing perspective can be found in Refs. 45 through 49. Preventing the Late Arrival of the Data Signal in a Local Data Path with Flip-Flops The operation of the local data path R i R f shown in Fig. 1.14 requires that any data signal that is being stored in R f arrives at the data input D f of R f no later than before the latching edge of the clock signal Cf. It is possible for the opposite event to occur, that is, for the data signal D f not to arrive at the register R f sufficiently early in order to be stored successfully within R f . If this situation occurs, the local data path shown in Fig. 1.14 fails to perform as expected and it is said that a timing failure or violation has been created. This form of timing violation is typically called a setup (or long path) violation. A setup violation is depicted in Fig. 1.15 and is used in the following discussion. The identical clock periods of the clock signals C i and C f are shaded for identification in Fig. 1.15. Also shaded in Fig. 1.15 are those portions of the data signals D i , Q i , and D f that are relevant to the operation of the local data path shown in Fig. 1.14. Specifically, the shaded portion of Di corresponds to the data to be stored in R i at the beginning of the k-th clock period. This data signal propagates to the output of the register R i and is illustrated by the shaded portion of Qi shown in Fig. 1.15. The combinational logic operates on Q i , during the k-th clock period. The result of this operation is the shaded portion of the signal Df which must be stored in R f during the next (k+1)-th clock period. Observe that, as illustrated in Fig. 1.15, the leading edge of C i that initiates the k-th clock period occurs at time kT CP . Similarly, the leading edge of C f that initiates the (k + 1)-th clock period occurs at time +(k+1) T CP . Therefore, the latest arrival time of D f at R f must satisfy (1.15) The term on the right-hand side of Eq. 1.15 corresponds to the critical situation of the leading edge of C f arriving earlier by the maximum possible deviation . The - term on the right-hand side of Eq. 1.15 accounts for the setup time of R f (recall the definition of ). Note that the value of in Eq. 1.15 consists of two components: 1. The latest arrival time that a valid data signal Q i appears at the output of R i : that is, the sum of the latest possible arrival time of the leading edge of C i and the maximum clock-to-Q delay of R i . 2. The maximum propagation delay of the data signals through the combinational logic block L if and interconnect along the path R i R f . Therefore, can be described as FIGURE 1.14 A single-phase local data path. 1-21System Timing (1.16) By substituting Eq. 1.16 into Eq. 1.15, the timing condition guaranteeing correct signal arrival at the data input D of R f is (1.17) The above inequality can be transformed by subtracting the terms from both sides of Eq. 1.17. Fur- thermore, certain terms in Eq. 1.17 can be grouped together and, by noting that - =T skew (i, f) is the clock skew between the registers R i and R f , (1.18) Note that a violation of Eq. 1.18 is illustrated in Fig. 1.15. The timing relationship Eq. 1.18 represents three important results describing the late arrival of the signal D f at the data input of the final register R f in a local data path R i R f : 1. Given any values of T skew (i, f) and the late arrival of the data signal at R f can be prevented by controlling the value of the clock period T CP . A sufficiently large value of T CP can always be chosen to relax Eq. 1.18 by increasing the upper bound described by the right- hand side of Eq. 1.18. FIGURE 1.15 Timing diagram of a local data path with flip-flops with violation of the setup constraint. 1-22 Memory, Microprocessor, and ASIC 2. For correct operation, the clock period T CP does not necessarily have to be larger than the term ( + + ). If the clock skew T Skew (i, f) is properly controlled, choosing a particular negative value for the clock skew will relax the left side of Eq. 1.18, thereby permitting Eq. 1.18 to be satisfied despite T CP -( + + ) < 0. 3. Both the term 2 and the term ( + + ) are harmful in the sense that these terms impose a lower bound on the clock period T CP (as expected). Although negative skew can be used to relax the inequality of Eq. 1.18, these two terms work against relaxing the values of T CP and T Skew (i,f) Finally, the relationship in Eq. 1.18 can be rewritten in a form that clarifies the upper bound on the clock skew T Skew (i, f) imposed by Eq. 1.18: (1.19) Preventing the Early Arrival of the Data Signal in a Local Data Path with Flip-Flops Late arrival of the signal D f at the data input of R f (see Fig. 1.14) was analyzed in the previous subsection. In this section, the analysis of the timing relationships of the local data path R i R f to prevent early data arrival of D f is presented. To this end, recall from previous discussion that any data signal D f being stored in R f must lag the arrival of the leading edge of C f by at least . It is possible for the opposite event to occur, that is, for a new data to overwrite the value of D f and be stored within the register R f . If this situation occurs, the local data path shown in Fig. 1.14 will not perform as desired because of a catastrophic timing violation known as a hold (or short path) violation. In this section, hold timing violations are analyzed. It is shown that a hold violation is more dangerous than a setup violation since a hold violation cannot be removed by simply adjusting the clock period T cp (unlike the case of a data signal arriving late where T CP can be increased to satisfy Eq. 1.18). A hold violation is depicted in Fig. 1.16, which is used in the following discussion. The situation depicted in Fig. 1.16 is different from the situation depicted in Fig. 1.15 in the following sense. In Fig. 1.15, a data signal stored in R i during the k-th clock period arrives too late to be stored in R f during the (k+1)-th clock period. In Fig. 1.16, however, the data stored in R i during the k-th clock period arrives at R f too early and destroys the data that had to be stored in R f during the same k-th clock period. To clarify this concept, certain portions of the data signals are shaded for easy identification in Fig. 1.16. The data D i being stored in R i at the beginning of the k-th clock period is shaded. This data signal propagates to the output of the register R i and is illustrated by the shaded portion of Q i shown in Fig. 1.16. The output of the logic (left unshaded in Fig. 1.16) is being stored within the register R f at the beginning of the (k+1)-th clock period. Finally, the shaded portion of D f corresponds to the data that must be stored in R f at the beginning of the k-th clock period. Note that, as illustrated in Fig. 1.16, the leading (or latching) edge of C i that initiates the k-th clock period occurs at time +kT CP . Similarly, the leading (or latching) edge of C f that initiates the k-th clock period occurs at time +kT CP . Therefore, the earliest arrival time of the data signal D f at the register R f must satisfy the following condition: (1.20) The term on the right-hand side of Eq. 1.20 corresponds to the critical situation of the leading edge of the k-th clock period of C f arriving late by the maximum possible deviation . Note that the value of in Eq. 1.20 has two components: 1. The earliest arrival time that a valid data signal Q i appears at the output of R i : that is, the sum of the earliest arrival time of the leading edge of C i and the minimum clock-to-Q delay of R i 2. The minimum propagation delay of the signals through the combinational logic block L if and interconnect wires along the path R i R f 1-23System Timing Therefore, can be described as (1.21) By substituting Eq. 1.21 into Eq. 1.20, the timing condition that guarantees that D f does not arrive too early at R f is (1.22) The inequality Eq. 1.22 can be further simplified by regrouping terms and noting that - = T Skew (i, f) is the clock skew between the registers R i and R f. (1.23) Recall that a violation of Eq. 1.23 is illustrated in Fig. 1.16. The timing relationship described by Eq. 1.23 provides certain important facts describing the early arrival of the signal D f at the data input of the final register R f of a local data path: 1. Unlike Eq. 1.18, the inequality Eq. 1.23 does not depend on the clock period T CP . Therefore, a violation of Eq. 1.23 cannot be corrected by simply manipulating the value of T CP . A synchronous digital system with hold violations is non-functional, while a system with setup violations will still operate correctly at a reduced speed.* For this reason, hold violations result in catastrophic * Increasing the clock period T CP in order to satisfy Eq. 1.18 is equivalent to reducing the frequency of the clock signal. FIGURE 1.16 Timing diagram of a local data path with flip-flops with a violation of the hold constraint. 1-24 Memory, Microprocessor, and ASIC timing failure and are considered significantly more dangerous than the setup violations previously described. 2. The relationship in Eq. 1.23 can be satisfied with a sufficiently large value of the clock skew T Skew (i, f). However, both the term 2 and the term are harmful in the sense that these terms impose a lower bound on the clock skew T Skew (i, f) between the registers R i and R f . Although positive skew may be used to relax Eq. 1.23, these two terms work against relaxing the values of T Skew (i, f) and Finally, the relationship in Eq. 1.23 can be rewritten to stress the lower bound imposed on the clock skew T Skew (i,f,) by Eq. 1.23: (1.24) 1.4.7 Analysis of a Single-Phase Local Data Path with Latches A local data path consisting of two level-sensitive registers (or latches) and the combinational logic between these registers (or latches) is shown in Fig. 1.17. Note the initial latch R i , which is the origin of the data signal, and the final latch R f , which is the destination of the data signal. The combinational logic block L if between R i and R f accepts the input data signals sourced by R i and other registers and logic gates and transmits the data signals that have been operated on to R f . The period of the clock signal is denoted by T CP and the delays of the clock signals C i and C f to the latches R i and R f are denoted by and respectively. The input and output data signals to R i and R f are denoted by D i , Q i , D f , and Q f , respectively. An analysis of the timing properties of the local data path shown in Fig. 1.17 is offered in the following sections. The timing relationships to prevent the late arrival of the data signal at the latch R f are examined, as well as the timing relationships to prevent the early arrival of the data signal at the latch R f . The analyses presented in this section build on assumptions regarding the timing relationships among the signals of a latch similar to those assumptions used in the previous chapter section. Specifically, it is guaranteed that every data signal arrives at the data input of a latch no later than time before the trailing clock edge. Also, this data signal must remain stable at least time after the trailing edge, that is, no new data signal should arrive at a latch time after the latch has become opaque. Observe the differences between a latch and a flip-flop. 45,50 Inflip-flops, the setup and hold requirements described in the previous paragraph are relative to the leading—not to the trailing—edge of the clock signal. Similar to flip-flops, the late and early arrival of the data signal to a latch give rise to timing violations known as setup and hold violations, respectively. Preventing the Late Arrival of the Data Signal in a Local Data Path with Latches A similar signal setup to the example illustrated in Fig. 1.15 is assumed in the following discussion. A data signal D i , is stored in the latch R i during the k-th clock period. The data Q i , stored in R i propagates through the combinational logic L if and the interconnect along the path R i R f . In the (k+1)-th FIGURE 1.17 A single-phase local data path with latches. 1-25System Timing clock period, the result D f of the computation in L if is stored within the latch R f . The signal D f must arrive at least time before the trailing edge of C f in the (k + 1)-th clock period. Similar to the discussion presented in the previous section, the latest arrival time of D f at the D input of R f must satisfy (1.25) Note the difference between Eqs. 1.25 and 1.15. In Eq. 1.15, the first term on the right-hand side is [ +(k + 1) T CP - ], while in Eq. 1.25, the first term on the right-hand side has an additional term . The addition of corresponds to the concept that, unlike flip-flops, a data signal is stored in a latch, shown in Fig. 1.17, at the trailing edge of the clock signal (the term). Similar to the case of flip-flops, the term on the right-hand side of Eq. 1.25 corresponds to the critical situation of the trailing edge of the clock signal C f arriving earlier by the maximum possible deviation . Observe that the value of in Eq. 1.25 consists of two components: 1. The latest arrival time when a valid data signal Q i appears at the output of the latch R i 2. The maximum signal propagation delay through the combinational logic block L if and the interconnect along the path R i R f Therefore, can be described as (1.26) However, unlike the situation of flip-flops discussed previously, the term on the right-hand side of Eq. 1.26 is not the sum of the delays through the register R i . The reason is that the value of depends on whether the signal D i arrived before or during the transparent state of R i in the k-th clock period. Therefore, the value of in Eq. 1.26 is the greater of the following two quantities: (1.27) There are two terms on the right-hand side of Eq. 1.27: 1. The term corresponds to the situation in which D i arrives at R i after the leading edge of the k-th clock period. 2. The term corresponds to the situation in which D i arrives at R i before the leading edge of the k-th clock pulse arrives. By substituting Eq. 1.27 into Eq. 1.26, the latest time of arrival is: (1.28) which is in turn substituted into Eq. 1.25 to obtain (1.29) Equation Eq. 1.29 is an expression for the inequality that must be satisfied in order to prevent the late arrival of a data signal at the data input D of the register R f . By satisfying Eq. 1.29, setup violations in the local data path with latches shown in Fig. 1.17 are avoided. For a circuit to operate correctly, Eq. 1.29 must be enforced for any local data path R i R f consisting of the latches R i and R f . 1-26 Memory, Microprocessor, and ASIC The max operation in Eq. 1.29 creates a mathematically difficult situation since it is unknown which of the quantities under the max operation is greater. To overcome this obstacle, this max operation can be split into two conditions: (1.30) (1.31) Taking into account that the clock skew T Skew (i, f)= - , Eqs. 1.30 and 1.31 can be rewritten as (1.32) (1.33) Equation 1.33 can be rewritten in a form that clarifies the upper bound on the clock skew T Skew (i, f) imposed by Eq. 1.33: (1.34) (1.35) Preventing the Early Arrival of the Data Signal in a Local Data Path with Latches A similar signal setup to the example illustrated in Fig. 1.16 is assumed in the discussion presented in this section. Recall the difference between the late arrival of a data signal at R f and the early arrival of a data signal at R f . In the former case, the data signal stored in the latch R i during the k-th clock period arrives too late to be stored in the latch R f during the (k+1)-th clock period. In the latter case, the data signal stored in the latch R i during the k-th clock period propagates to the latch R f too early and overwrites the data signal that was already stored in the latch R f during the same k-th clock period. In order for the proper data signal to be successfully latched within R f during the k-th clock period, there should not be any changes in the signal D f until at least the hold time after the arrival of the storing (trailing) edge of the clock signal C f . Therefore, the earliest arrival time of the data signal D f at the register R f must satisfy the following condition: (1.36) The term on the right-hand side of Eq. 1.36 corresponds to the critical situation of the trailing edge of the k-th clock period of the clock signal C f arriving late by the maxiumum possible deviation . Note that the value of in Eq. 1.36 consists of two components: 1. The earliest arrival time that a valid data signal Q i appears at the output of the latch R i : that is, the sum of the earliest arrival time of the leading edge of the clock signal C i and the minimum clock-to-Q delay of R f 2. The minimum propagation delay of the signal through the combinational logic L if and the interconnect along the path R i R f Therefore, can be described as (1.37) By substituting Eq. 1.37 into Eq. 1.36, the timing condition guaranteeing that D f does not arrive too early at the latch R f is 1-27System Timing (1.38) The inequality Eq. 1.38 can be further simplified by reorganizing the terms and noting that - =T Skew (i, f) is the clock skew between the registers R i and R f : (1.39) The timing relationship described by Eq. 1.39 represents two important results describing the early arrival of the signal D f at the data input of the final latch R f of a local data path: 1. The relationship in Eq. 1.39 does not depend on the value of the clock period T CP . Therefore, if a hold timing violation in a synchronous system has occurred,* this timing violation is catastrophic. 2. The relationship in Eq. 1.39 can be satisfied with a sufficiently large value of the clock skew T Skew (i, f). Furthermore, both the term ( + ) and the term are harmful in the sense that these terms impose a lower bound on the clock skew T Skew (i, f) between the latches R j and R f . Although positive skew T Skew (i, f)>0 can be used to relax Eq. 1.39, these two terms make it difficult to satisfy the inequality in Eq. 1.39 for specific values of T Skew (i, f) and ( + ). Furthermore, Eq. 1.39 can be rewritten to emphasize the lower bound on the clock skew T Skew (i, f) imposed by Eq. 1.39: (1.40) 1.5 A Final Note The properties of registers and local data paths were described in this chapter. Specifically, the timing relationships to prevent setup and hold timing violations in a local data path consisting of two positive edge-triggered flip-flops were analyzed. The timing relationships to prevent setup and hold timing violations in a local data path consisting of two positive-polarity latches were also analyzed. In a fully synchronous digital VLSI system, however, it is possible to encounter types of local data paths different from those circuits analyzed in this chapter. For example, a local data path may begin with a positive-polarity, edge-sensitive register R i , and end with a negative-polarity, edge-sensitive register R f . It is also possible that different types of registers are used; for example, a register with more than one data input. In each individual case, the analyses described in this chapter illustrate the general methodology used to derive the proper timing relationships specific to that system. Furthermore, note that for a given system, the timing relationships that must be satisfied for the system to operate correctly—such as Eqs. 1.19, 1.24, 1.34, 1.35, and 1.40—are collectively referred to as the overall timing constraints of the synchronous digital system. 13,51-55 1.6 Glossary of Terms The following notations are used in this chapter. 1. Clock Signal Parameters T CP : The clock period of a circuit D L : The tolerance of the leading edge of any clock signal ∆ T : The tolerance of the trailing edge of any clock signal * As described by the inequality Eq. 1.39 not being satisfied. 1-28 Memory, Microprocessor, and ASIC The tolerance of the leading edge of a clock signal driving a latch The tolerance of the trailing edge of a clock signal driving a latch The tolerance of the leading edge of a clock signal driving a flip-flop The tolerance of the trailing edge of a clock signal driving a flip-flop The minimum width of the clock signal in a circuit with latches The minimum width of the clock signal in a circuit with flip-flops 2. Latch Parameters The clock-to-output delay of a latch The clock-to-output delay of the latch R i The minimum clock-to-output delay of a latch The minimum clock-to-output delay of the latch R i The maximum clock-to-output delay of a latch The maximum clock-to-output delay of the latch R i The data-to-output delay of a latch The data-to-output delay of the latch R i The minimum data-to-output delay of a latch The minimum data-to-output delay of the latch R i The maximum data-to-output delay of a latch The maximum data-to-output delay of the latch R i The setup time of a latch The setup time of the latch R i The hold time of a latch The hold time of the latch R i The latest arrival time of the data signal at the data input of a latch The latest arrival time of the data signal at the data input of the latch R i The earliest arrival time of the data signal at the data input of a latch The earliest arrival time of the data signal at the data input of the latch R i The latest arrival time of the data signal at the data output of a latch The latest arrival time of the data signal at the data output of the latch R i The earliest arrival time of the data signal at the data output of a latch The earliest arrival time of the data signal at the data output of the latch R i 3. Flip-flop Parameters The clock-to-output delay of a latch The clock-to-output delay of the latch R i The minimum clock-to-output delay of a flip-flop The minimum clock-to-output delay of the flip-flop R i The maximum clock-to-output delay of a flip-flop The maximum clock-to-output delay of the flip-flop R i 1-29System Timing The setup time of a flip-flop The setup time of the flip-flop R i The hold time of a flip-flop The hold time of the flip-flop R i The latest arrival time of the data signal at the data input of a flip-flop The latest arrival time of the data signal at the data input of the flip-flop R i The earliest arival time of the data signal at the data input of a flip-flop The earliest arrival time of the data signal at the data input of the flip-flop R i The latest arrival time of the data signal at the data output of a flip-flop The latest arival time of the data signal at the data output of the flip-flop R i The earliest arrival time of the data signal at the data output of a flip-flop The earliest arrival time of the data signal at the data output of the flip-flop R i 4. Local Data Path Parameters R i ?RightArrow-? R f : A local data path from register R i to register R f exists R i ?RightArrow-? R f : A local data path from register R i to register R f does not exist References 1. Kilby, J.S., “Invention of the Integrated Circuit,” IEEE Transactions on Electron Devices, vol. ED-23, pp. 648–654, July 1976. 2. Rabaey, J.M., Digital Integrated Circuits: A Design Perspective. Prentice Hall, Inc., Upper Saddle River, NJ, 1995. 3. Gaddis, N. and Lotz, J., “A 64-b Quad-Issue CMOS RISC Microprocessor,” IEEE Journal of Solid-State Circuits, vol. SC-31, pp. 1697–1702, Nov. 1996. 4. Gronowski, P.E. et al., “A 433-MHz 64-bit Quad-Issue RISC Microprocessor,” IEEE Journal of Solid-State Circuits, vol. SC-31, pp. 1687–1696, Nov. 1996. 5. Vasseghi, N., Yeager, K., Sarto, E., and Seddighnezhad, M., “200-Mhz Superscalar RISC Microprocessor,” IEEE Journal of Solid-State Circuits, vol. SC-31, pp. 1675–1686, Nov. 1996. 6. Bakoglu, H.B., Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley Publishing Company, Reading, MA, 1990. 7. Bothra, S., Rogers, B., Kellam, M., and Osburn, C.M., “Analysis of the Effects of Scaling on Interconnect Delay in ULSI Circuits,” IEEE Transactions on Electron Devices, vol. ED-40, pp. 591– 597, Mar. 1993. 8. Weste, N.W. and Eshraghian, K., Principles of CMOS VLSI Design: A Systems Perspective. Addison- Wesley Publishing Company, Reading, MA, 2nd ed., 1992. 9. Mead, C. and Conway, L., Introduction to VLSI Systems. Addison-Wesley Publishing Company, Reading, MA, 1980. 10. Anceau, F., “ASynchronous Approach for Clocking VLSI Systems,” IEEE Journal of Solid-State Circuits, vol. SC-17, pp. 51–56, Feb. 1982. 11. Afghani M. and Svensson, C., “A Unified Clocking Scheme for VLSI Systems,” IEEE Journal of Solid State Circuits, vol. SC-25, pp. 225–233, Feb. 1990. 12. Unger, S.H. and Tan, C-J., “Clocking Schemes for High-Speed Digital Systems,” IEEE Transactions on Computers, vol. C 35, pp. 880–895, Oct. 1986. 13. Friedman, E.G., Clock Distribution Networks in VLSI Circuits and Systems. IEEE Press, 1995. [...]... Circuits and Systems, pp 12 17, Dec 19 92 28 Kourtev, I.S and Friedman, E.G., “Simultaneous Clock Scheduling and Buffered Clock Tree Synthesis,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp 18 12 1815, June 1997 29 Neves, J.L and Friedman, E.G.,“Optimal Clock Skew Scheduling Tolerant to ProcessVariations,” Proceedings of the 33rd ACM/IEEE Design Automation Conference, pp 623 – 628 ,... corresponding to the memory contents ROM/PROM/EPROM FIGURE 2. 2 Geometry-variable multiple-valued NOR ROM FIGURE 2. 3 ROM sense amplifier 2- 3 Memory, Microprocessor, and ASIC 2- 4 2. 2.3 Architecture Constructing large ROMs with fast access times requires the memory array to be divided into smaller memory banks.This gives rise to the concept of divided word lines and divided bit lines that reduces the capacitance... the bitline are potentially very slow .2 0–8493–1737–1/03/$0.00+$1.50 © 20 03 by CRC Press LLC 2- 1 Memory, Microprocessor, and ASIC 2- 2 FIGURE 2. 1 The ROM market growth and forecast Encoding multiple-valued data in the memory array involves a one-to-one mapping of logic value to transistor characteristics at each memory location and can be implemented in two ways: (i) Adjust the width-to-length (W/L)... Specification and Synthesis of Digital Systems, pp 131–141, Nov 1995 56 Deokar, R.R and Sapatnekar, S.S., “A Fresh Look at Retiming via Clock Skew Optimization,” Proceedings of the 32nd ACM/IEEE Design Automation Conference, pp 310–315, June 1995 2 ROM/PROM/EPROM 2. 1 Introduction 2. 2 ROM 2- 1 2- 1 Core Cells • Peripheral Circuitry • Architecture 2. 3 Jen-Sheng Hwang National Science Council PROM 2- 4 Read-Only... Mar 1995 21 Ito, N., Sugiyama, H., and Konno,T., “ChipPRISM: Clock Routing and Timing Analysis for HighPerformance CMOSVLSI Chips,” Fujitsu Scientific andTechnical Jornal, vol 31, pp 180–187, Dec 1995 22 Leiserson, C.E and Saxe, J.B.,“A Mixed-Integer Linear Programming Problem Which Is Efficiently Solvable,” Journal of Algorithms, vol 9, pp 114– 128 , Mar 1988 23 Cormen, T.H., Leiserson, C.E., and Rivest,... the array, as indicated in Fig 2. 4 This line contains “0”s on all 25 6 cells and has the longest discharge time It is used to generate timing for a delayed enable signal that activates the sense amplifier circuits These circuits were used for all types of ROM to provide a fair comparison of the performance of each type of ROM.5 2- 6 Memory, Microprocessor, and ASIC 2. 3 .2 Conventional Diffusion Programming... required.5 2. 3.3 Conventional VIA -2 Contact Programming ROM In order to obtain better fabrication cycle time, conventional VIA -2 contact programming ROM was used as shown in Fig 2. 7 Cell-C in Fig 2. 7(a) is coding “1”; Cell-D is coding “1” There are determined by VIA -2 code existence on bit cells.The VIA -2 is final stage of process and base process can be completed just before VIA -2 etching and remaining... is critical for 100 MIPS DSP.5 2. 3.4 New VIA -2 Contact Programming ROM The new architecture VIA -2 programming ROM is shown in Fig 2. 8 A complex matrix constructs each 8-bit block with GND on each side Cell-E in Fig 2. 8(a) is coding “0” Bit 4 and N4 are connected by VIA -2 Cell-F is coding “1” since Bit 5 and N5 are disconnected Coding other bit lines (Bit 0, 1, 2, 3,5, 6, and 7) follows the same procedure... of DWL and HWD (From Hirose, T et al., IEEE J Solid-State Circuits, 25 , 5, 1068, 1990 With permission.) FIGURE 3. 12 Two-stage current-mirror sense amplifier (From Itoh, K., Sasaki, K., and Nakagome,Y., Proc of the IEEE, 524 , 1995 With permission.) 3-10 Memory, Microprocessor, and ASIC asserted for a period of time, enough to amplify the small difference on data lines; then it is deactivated and the... architecture VIA -2 contact programming ROM for QLM and PLM processes has simple processing with high density which obtains excellent results targeting 2. 5V and 2. 0V supply voltage 2. 3.1 Read-Only Memory Module Architecture The details of the ROM module configuration are shown in Fig 2. 4 This ROM has a single access mode (16-bit data read from half of ROM array) and a dual access mode ( 32- bit data read . 1 -20 Memory, Microprocessor, and ASIC signal C i and C f to the flip-flops R i and R f are denoted by and , respectively. The input and output data signals to R i and R f are. Automation Conference, pp. 310–315, June 1995. 2- 1 2 ROM/PROM/EPROM 2. 1 Introduction 2- 1 2. 2 ROM 2- 1 Core Cells • Peripheral Circuitry • Architecture 2. 3 PROM 2- 4 Read-Only Memory Module Architecture. performance of each type of ROM. 5 FIGURE 2. 5 Detail of low power selective bit line precharge and sense amplifier circuits. 2- 6 Memory, Microprocessor, and ASIC 2. 3 .2 Conventional Diffusion Programming