1 NATIONAL UNIVERSITY OF HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING LECTURE Lecturer: Lam Duc Khai VERILOG Hardware Design Language Chapter7: Tasks and Functions Subject: 2 Agenda 1. Chapter 1: Introduction ( Week1) 2. Chapter 2: Fundamental concepts (Week1) 3. Chapter 3: Modules and hierarchical structure (Week2) 4. Chapter 4: Primitive Gates – Switches – User defined primitives (Week2) 5. Chapter 5: Structural model (Week3) 6. Chapter 6: Behavioral model – Combination circuit & Sequential circuit (Week4 & Week5) 7. Chapter 7: Tasks and Functions (Week6) 8. Chapter 8: State machines (Week6) 9. Chaper 9: Testbench and verification (Week7) 3 Tasks versus Functions in Verilog • Procedures/Subroutines/Functions in SW programming languages – The same functionality, in different places • Verilog equivalence: – Tasks and Functions – function and task (~ function and subroutine) – Used in behavioral modeling – Part of design hierarchy ⇒ Hierarchical name 4 Differences between • Functions – Can enable (call) just another function (not task) – Execute in 0 simulation time – No timing control statements allowed ( next slide ) – At lease one input – Return only a single value • Tasks – Can enable other tasks and functions – May execute in non-zero simulation time – May contain any timing control statements – May have arbitrary input, output, or inouts – Do not return any value 5 Timing Control • Delay # Used to delay statement by specified amount of simulation time • Event Control @ Delay execution until event occurs Event may be single signal/expression change Multiple events linked by or always begin #10 clk = 1; #10 clk = 0; end always @(posedge clk) begin q <= d; end always @(x or y) begin s = x ^ y; c = x & y;; end 6 Differences between… (cont’d) • Both – are defined in a module – are local to the module – can have local variables (registers, but not nets) and events – contain only behavioral statements (NOT continuous statements) – do not contain initial or always statements – are called from initial or always statements or other tasks or functions 7 Differences between… (cont’d) • Tasks can be used for common Verilog code • Function are used when the common code – is purely combinational – executes in 0 simulation time – provides exactly one output • Functions are typically used for conversions and commonly used calculations 8 Tasks • Keywords: task, endtask • Must be used if the procedure has – any timing control constructs – zero or more than one output arguments – no input arguments 9 Tasks (cont’d) • Task declaration and invocation – Declaration syntax task <task_name>; <I/O declarations> <variable and event declarations> begin // if more than one statement needed <statement(s)> end // if begin used! endtask 10 Tasks (cont’d) • Task declaration and invocation – Task invocation syntax <task_name>; <task_name> (<arguments>); – input and inout arguments are passed into the task – output and inout arguments are passed back to the invoking statement when task is completed [...]... ?(address1); end endfunction endmodule 19 Tasks and Functions Summary • Tasks and functions in behavioral modeling – The same purpose as subroutines in SW – Provide more readability, easier code management – Are part of design hierarchy – Tasks are more general than functions • Can represent almost any common Verilog code – Functions can only model purely combinational calculations.. .Tasks (cont’d) • I/O declaration in modules vs tasks – Both used keywords: input, output, inout – In modules, represent ports • connect to external signals – In tasks, represent arguments • pass values to and from the task 11 Task Examples: Use of input and output arguments module operation; parameter delay = 10; reg [15:0] A, B; reg [15:0] AB _AND, AB_OR, AB_XOR; initial... if begin used endfunction 15 Functions (cont’d) • Function Declaration and Invocation – Invocation syntax: (); 16 Functions (cont’d) • Semantics – much like function in Pascal – An internal implicit reg is declared inside the function with the same name – The return value is specified by setting that implicit reg – defines width and type of the implicit reg... delay = 10; reg [15:0] A, B; reg [15:0] AB _AND, AB_OR, AB_XOR; initial $monitor( …); initial begin … end always @(A or B) begin bitwise_oper(AB _AND, AB_OR, AB_XOR, A, B); end task bitwise_oper; output [15:0] ab _and, ab_or, ab_xor; input [15:0] a, b; begin #delay ab _and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask endmodule 12 Task Examples : Use of module local variables module sequence; reg clock;... clock = 1'b1; #3 clock = 1'b0; #10 clock = 1'b1; end endtask endmodule 13 Functions • Keyword: function, endfunction • Can be used if the procedure – – – – does not have any timing control constructs returns exactly a single value does not have any output has at least one input argument 14 Functions (cont’d) • Function Declaration and Invocation – Declaration syntax: function ; . Chapter 7: Tasks and Functions (Week6) 8. Chapter 8: State machines (Week6) 9. Chaper 9: Testbench and verification (Week7) 3 Tasks versus Functions in Verilog • Procedures/Subroutines /Functions. equivalence: – Tasks and Functions – function and task (~ function and subroutine) – Used in behavioral modeling – Part of design hierarchy ⇒ Hierarchical name 4 Differences between • Functions –. (address>>1); end endfunction endmodule The implicit reg 32 bit width 20 Tasks and Functions Summary • Tasks and functions in behavioral modeling – The same purpose as subroutines in SW – Provide