Design and Implementation of VLSI Systems Lecture 03 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 03: CMOS FABRICATION 2 Fabricating One Inverter 1 Layout & Design Rule Check 2 Stick Diagram 3 Euler path 4 LECTURE 03: CMOS FABRICATION 3 Fabricating One Inverter 1 Layout & Design Rule Check 2 Stick Diagram 3 Euler path 4 4 REVIEW n+ p GateSource Drain bulk Si SiO 2 Polysilicon n+ Body SiO 2 n GateSource Drain bulk Si Polysilicon p+ p+ nMOS pMOS WAFER PREPARATION 5 CMOS FABRICATION  CMOS transistors are fabricated on silicon wafer  Lithography process similar to printing press  On each step, different materials are deposited or etched  Easiest to understand by viewing both top and cross- section of wafer in a simplified manufacturing process 6 EXAMPLE: INVERTER 7 8 Cross-Section View Top View n+ p substrate p+ n well A Y GND V DD n+p+ substrate tap well tap n+ p+ GND V DD Y A substrate tap well tap nMOS transistor pMOS transistor INVERTER CROSS-SECTION  Typically use p-type substrate for nMOS transistors  Requires n-well for body of pMOS transistors n+ p substrate p+ n well A Y GND V DD n+ p+ SiO 2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor 9 WELL AND SUBSTRATE TAPS  Substrate must be tied to GND and n-well to V DD  Metal to lightly-doped semiconductor forms poor connection called Shottky Diode  Use heavily doped well and substrate contacts / taps n+ p substrate p+ n well A Y GND V DD n+p+ substrate tap well tap n+ p+ 10 [...]... structures must obey the dimensions and separation rules dictated by the process fabrication facility 33 SUMMARY OF TERMINOLOGY (CONT.) 34 LECTURE 03: CMOS FABRICATION 1 Fabricating One Inverter 2 Layout & Design Rule Check 3 Stick Diagram 4 Euler path 35 2.1 LAYOUT Chips are specified with set of masks  Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)  36 ... field oxide p+ n+ n+ p+ p+ n+ n well p substrate 30 CROSS SECTION OF A 7-METAL LAYER IC 31 SUMMARY OF TERMINOLOGY • body • diffusion (n/p) • source • drain • well • polysilicon gate • length/width • gate oxide • channel  All these structures must obey the dimensions and separation rules dictated by the process fabrication facility 32 SUMMARY OF • well • tap • contact • metal track TERMINOLOGY (CONT.) •... Implanatation Blast wafer with beam of As ions  Ions blocked by SiO2, only enter exposed Si  SiO2 n well 20 STRIP OXIDE Strip off the remaining oxide using HF  Back to bare wafer with n-well  Subsequent steps involve similar series of steps  n well p substrate 21 POLYSILICON  Deposit very thin layer of gate oxide   < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer... ion implantation today  But regions are still called diffusion  n+ n+ n+ n well p substrate 26 N-DIFFUSION (CONT.)  Strip off oxide to complete patterning step n+ n+ n+ n well p substrate 27 P-DIFFUSION  Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ n well p substrate 28 CONTACTS Now we need to wire together the devices... SiO2 on top of Si wafer  900 – 1200 C with H2O or O2 in oxidation furnace SiO2 p substrate 15 PHOTORESIST  Spin on photoresist   Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist SiO2 p substrate 16 LITHOGRAPHY Expose photoresist through n-well mask  Strip off exposed photoresist  Photoresist SiO2 p substrate 17 ETCH  Etch oxide with hydrofluoric acid... football fields  Courtesy of International Business Machines Corporation Unauthorized use not permitted 13 FABRICATION STEPS Start with blank wafer  Build inverter from the bottom up  First step will be to form the n-well  Cover wafer with protective layer of SiO2 (oxide)  Remove layer where n-well should be built  Implant or diffuse n dopants into exposed wafer  Strip off SiO2  p substrate 14... pattern polysilicon Polysilicon Polysilicon Thin gate oxide n well p substrate 23 SELF-ALIGNED PROCESS Use oxide and masking to expose where n+ dopants should be diffused or implanted  N-diffusion forms nMOS source, drain, and n-well contact  n well p substrate 24 N-DIFFUSION Pattern oxide and form n+ regions  Self-aligned process where gate blocks diffusion  Polysilicon is better than metal for self-aligned... photoresist  Photoresist SiO2 p substrate 17 ETCH  Etch oxide with hydrofluoric acid (HF)   Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist SiO2 p substrate 18 STRIP PHOTORESIST  Strip off remaining photoresist   Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step SiO2 p substrate 19 N-WELL n-well is...INVERTER MASK SET Transistors and wires are defined by masks  Cross-section taken along dashed line  A Y GND VDD nMOS transistor substrate tap pMOS transistor well tap 11 DETAILED MASK VIEWS  Six masks n-well  Polysilicon  n+ diffusion  p+ diffusion  Contact  Metal n well  Polysilicon n+ Diffusion p+ Diffusion Contact Metal 12 FABRICATION Chips are built in huge factories called . Design and Implementation of VLSI Systems Lecture 03 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 03: CMOS FABRICATION. One Inverter 1 Layout & Design Rule Check 2 Stick Diagram 3 Euler path 4 LECTURE 03: CMOS FABRICATION 3 Fabricating One Inverter 1 Layout & Design Rule Check 2 Stick. Si SiO 2 Polysilicon n+ Body SiO 2 n GateSource Drain bulk Si Polysilicon p+ p+ nMOS pMOS WAFER PREPARATION 5 CMOS FABRICATION  CMOS transistors are fabricated on silicon wafer  Lithography process similar to printing