Design and Implementation of VLSI Systems Lecture 04 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 04: MOS TRANSISTOR THEORY 2 Ideal (Shockley) Model 1 Non-ideal Model 2 DC Transfer Characteristics 3 LECTURE 04: MOS TRANSISTOR THEORY 3 Ideal (Shockley) Model 1 Non-ideal Model 2 DC Transfer Characteristics 3 IDEAL (SHOCKLEY) MODEL  A silicon p–n junction with no applied voltage. 4 Review: p-n junction  A p–n junction in thermal equilibrium with zero bias voltage applied 5  A p–n junction in thermal equilibrium with zero bias voltage applied. Under the junction, plots for the charge density, the electric field and the voltage are reported. 6 GATE-OXIDE-BODY SANDWICH = CAPACITOR polysilicon gate (a) silicon dioxide insulator p-type body + - V g < 0 (b) + - 0 < V g < V t depletion region (c) + - V g > V t depletion region inversion region 7 Operating modes • Accumulation • Depletion • Inversion •The charge accumulated is proportional to the excess gate-channel voltage (V gc -V t ) NMOS CUTOFF  No channel  I ds ≈ 0 + - V gs = 0 n+ n+ + - V gd p-type body b g s d 8 NMOS LINEAR  Channel forms  Current flows from d to s  e - from s to d  I ds increases with V ds  Similar to linear resistor + - V gs > V t n+ n+ + - V gd = V gs + - V gs > V t n+ n+ + - V gs > V gd > V t V ds = 0 0 < V ds < V gs -V t p-type body p-type body b g s d b g s d I ds 9 NMOS SATURATION  Channel pinches off  I ds independent of V ds  We say current saturates  Similar to current source + - V gs > V t n+ n+ + - V gd < V t V ds > V gs -V t p-type body b g s d I ds 10 [...]...THE MOS TRANSISTOR HAS THREE REGIONS OF OPERATION  Cut off Vgs < Vt o Linear (resistor) Vgs > Vt & Vds < VSAT = Vgs-Vt Current prop to Vds NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V o Saturation Vgs > Vt and Vds ≥ VSAT = Vgs-Vt Current is independent of Vds 11 HOW TO CALCULATE THE CURRENT VALUE?  MOS structure looks like parallel plate... saturation for pMOS 22 Covered ideal (long channel) operation (Shockley model) of transistor LECTURE 04: MOS TRANSISTOR THEORY 1 Ideal (Shockley) Model 2 Non-ideal Model 3 DC Transfer Characteristics 23 IDEAL VS NON-IDEAL ideal Non-ideal  Saturation current does not increase quadratically with Vgs  Saturation current lightly increases with increase in Vds 24  There is leakage current when the transistor. .. Vt if we increase/decrease the body bias? 34 PROCESS VARIATIONS Both MOSFETs have 30nm channel with 130 dopant atoms in the channel depletion region threshold voltage 0.97V threshold voltage 0.57V Process variations impact gate length, threshold voltage, and oxide thickness 35 SUMMARY OF TRANSISTOR OPERATION NMOS transistor PMOS transistor 36 ...  Vt  (VGS > VT AND VDS ≥ V  ds  V  dsat  pinched off 2  Now drain voltage no longer increases current 16 OPERATION MODES SUMMARY   0   V I ds    Vgs  Vt  ds  2   2   Vgs  Vt    2 Vgs  Vt V V  V  ds ds dsat  Vds  Vdsat cutoff linear saturation β: transconductance parameter of transistor 17 CURRENT-VOLTAGE RELATIONS β: transconductance parameter of transistor W/L: width-to-length... Subthreshold leakage is the biggest source in modern transistors Vgs Vt I ds  I ds 0e nvT 2 I ds 0   vT e1.8 Vds  v 1  e T   n = 1.4-15 Boltzmann distribution     180nm process 30 LEAKAGE CURRENT: JUNCTION LEAKAGE AND TUNNELING Junction leakage: reverse-biased p-n junctions have some leakage Is depends on doping levels and area and perimeter of diffusion regions p+ n+ n+ p+  VD  vT I D ... Vds diminishes in effect (more voltage drop)  takes longer to push carriers across the transistor  reducing current flow  18 TRANSISTOR CAPACITANCE  Gate capacitance: to body + to drain + to source  Diffusion capacitance: source-body and drain-body capacitances 19 GATE CAPACITANCE AS A FUNCTION OF VGS QuickTime™ and a decompressor are needed to see this picture 20 SOURCE/DRAIN DIFFUSION CAPACITANCE... for older processes (and future processes with high-k dielectrics!) 0.6 nm 0.8 nm 2 J (A/cm ) G 10 6 VDD trend 10 3 1.0 nm 1.2 nm 10 0 1.5 nm 1.9 nm 10 -3 10 -6 10 -9 0 0.3 0.6 0.9 VDD 1.2 1.5 1.8 31 IMPACT OF TEMPERATURE o Carrier mobility decreases with To↑ o Threshold voltage decreases nearly linearly with To ↑ o Junction leakage increases with To ↑ o ON current decreases and OFF current increases... on area and perimeter W     Use small diffusion nodes Comparable to Cg Varies with process Channel-stop implant N A1 Side wall Source ND Bottom xj Side wall LS Channel Substrate A N 21 SUMMARY OF SHOCKLEY MODEL polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, ox = 3.9) p-type body   0   V I ds    Vgs  Vt  ds  2   2   Vgs  Vt     2 for nMOS Vgs  Vt cutoff V V... leakage current when the transistor is in cut off  Ids depends on the temperature 25 At high electric field, drift velocity rolls of due to carrier scattering u n ( m /s ) VELOCITY SATURATION usat= 105 Constant velocity Constant mobility (slope = µ) xc = 1.5 x (V/µm) Empirically: 26 ALPHA MODEL  0  V  I ds   I dsat ds Vdsat   I dsat  Vgs  Vt cutoff Vds  Vdsat linear Vds  Vdsat saturation... cutoff Vds  Vdsat linear Vds  Vdsat saturation I dsat  Pc  V 2 gs  Vt   Vdsat  Pv Vgs  Vt   /2 Pc, Pv and alpha are found by fitting the model to the empirical modeling results 27 MOBILITY DEGRADATION 28 CHANNEL LENGTH MODULATION • The reverse-bias p-n junction between drain and body forms a depletion region with a width Ld that increases with Vdb GND Source VDD Gate VDD Drain Depletion . Design and Implementation of VLSI Systems Lecture 04 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 04: MOS TRANSISTOR. Spring 2011 1 LECTURE 04: MOS TRANSISTOR THEORY 2 Ideal (Shockley) Model 1 Non-ideal Model 2 DC Transfer Characteristics 3 LECTURE 04: MOS TRANSISTOR THEORY 3 Ideal (Shockley) Model 1. > V t and V ds ≥ V SAT = V gs -V t Current is independent of V ds NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V HOW TO CALCULATE THE CURRENT VALUE?  MOS structure