Design and Implementation of VLSI Systems Lecture 07 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 07: SEQUENTIAL CIRCUIT DESIGN Introduction 1 Circuit Design of Latches and Flip-flops 2 Sequencing Static Circuits 3 2 Static Sequencing Element Methodology 4 Synchronizer 5 LECTURE 07: SEQUENTIAL CIRCUIT DESIGN Sequencing 1 Sequencing Element Design 2 Sequencing Methods 3 3 Introduction 1 Circuit Design of Latches and Flip-flops 2 Sequencing Static Circuits 3 Static Sequencing Element Methodology 4 Synchronizer 5 SEQUENCING  Combinational logic  Output depends on current inputs  Sequential logic  Output depends on current and previous inputs  Requires separating previous, current, future  Called state or tokens  Ex: FSM, pipeline CL clk in out clk clk clk CL CL PipelineFinite State Machine 4 SEQUENCING (CONT.)  If tokens moved through pipeline at constant speed, no sequencing elements would be necessary  Ex: fiber-optic cable  Light pulses (tokens) are sent down cable  Next pulse sent before first reaches end of cable  No need for hardware to separate pulses  But dispersion sets min time between pulses  This is called wave pipelining in circuits  In most circuits, dispersion is high  Delay fast tokens so they don’t catch slow ones. 5 SEQUENCING OVERHEAD  Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.  Inevitably adds some delay to the slow tokens  Makes circuit slower than just the logic delay  Called sequencing overhead  Some people call this clocking overhead  But it applies to asynchronous circuits too  Inevitable side effect of maintaining sequence 6 LECTURE 07: SEQUENTIAL CIRCUIT DESIGN Sequencing 1 Sequencing Element Design 2 Sequencing Methods 3 7 Introduction 1 Circuit Design of Latches and Flip-flops 2 Sequencing Static Circuits 3 Static Sequencing Element Methodology 4 Synchronizer 5 SEQUENCING ELEMENTS  Latch: Level sensitive  a.k.a. transparent latch, D latch  Flip-flop: edge triggered  A.k.a. master-slave flip-flop, D flip-flop, D register  Timing Diagrams  Transparent  Opaque  Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop) D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop) 8 LATCH DESIGN  Pass Transistor Latch  Pros + Tiny + Low clock load  Cons  V t drop  nonrestoring  backdriving  output noise sensitivity  dynamic  diffusion input D Q  Used in 1970’s 9 LATCH DESIGN  Transmission gate + No V t drop - Requires inverted clock D Q   10 [...]... reset    19 SET/RESET Set forces output high when enabled  Flip-flop with asynchronous set and reset    reset set D    Q  set reset   20 LECTURE 07: SEQUENTIAL CIRCUIT DESIGN 1 Introduction Sequencing 2 Circuit Design of Latches and Sequencing Element Design Flip-flops 3 Sequencing Methods Static Circuits 4 Static Sequencing Element Methodology 5 Synchronizer 21 SEQUENCING METHODS Tc clk...LATCH DESIGN  Inverting buffer + Restoring + No backdriving + Fixes either  Output noise sensitivity  Or diffusion input    Inverted output X D Q  D Q  11 LATCH DESIGN  Tristate feedback + Static  Backdriving risk   Static latches are now essential because of leakage X D  Q   12 LATCH DESIGN   Buffered input + Fixes diffusion input + Noninverting X D  Q   13 LATCH DESIGN  ... LATCH DESIGN   Buffered output + No backdriving X D   Q  Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading  14 LATCH DESIGN  Datapath latch + smaller + faster - unbuffered input  Q X D    15 FLIP-FLOP DESIGN  Flip-flop is built as pair of back-to-back latches   X D Q     Q X D  Q      16 PULSE GENERATOR... D Q     Q X D  Q      16 PULSE GENERATOR 17 ENABLE Enable: ignore clock when en = 0 Mux: increase latch D-Q delay  Clock Gating: increase en setup time, skew  Symbol Multiplexer Design Clock Gating Design  en D 1 Q 0 en Q D  en 1 0 Q Q D en Flop D Flop  en Q en  D Latch  Latch D Latch  Flop  Q 18 RESET Force output low when reset asserted  Synchronous vs asynchronous   Q D reset... Combinational Logic Latch p Latch Pulsed Latches p tnonoverlap Tc/2 2 Latch 2-Phase Transparent Latches 1 Latch Flip-Flops Flip-flops  2-Phase Latches  Pulsed Latches  clk 22 TIMING DIAGRAMS Contamination and Propagation Delays tpd Logic Prop Delay tcd Logic Cont Delay tpcq Latch/Flop Clk->Q Prop Delay tccq Latch/Flop Clk->Q Cont Delay tpdq Latch D->Q Prop Delay tcdq Latch D->Q Cont Delay tsetup Latch/Flop... 2-PHASE LATCHES L1 1 Q1 CL Hold time reduced by nonoverlap 2 1 Paradox: hold applies twice each cycle, vs only once for flops L2 D2 tcd 1,tcd 2  thold  tccq  tnonoverlap tnonoverlap But a flop is made of two latches! tccq 2 Q1 D2 tcd thold 29 MIN-DELAY: PULSED LATCHES L1 p tcd  thold  tccq  t pw Q1 CL Hold time increased by pulse width D2 p L2 p tpw thold Q1 tccq D2 tcd 30 TIME BORROWING  In... setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system Data can pass through latch while transparent  Long cycle of logic can borrow time into next  As long as each loop completes in one cycle  31 TIME BORROWING EXAMPLE 1 2 Combinational Logic Borrowing time across half-cycle boundary Combinational Logic Borrowing . Design and Implementation of VLSI Systems Lecture 07 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 07: SEQUENTIAL. maintaining sequence 6 LECTURE 07: SEQUENTIAL CIRCUIT DESIGN Sequencing 1 Sequencing Element Design 2 Sequencing Methods 3 7 Introduction 1 Circuit Design of Latches and Flip-flops 2 Sequencing. SEQUENTIAL CIRCUIT DESIGN Introduction 1 Circuit Design of Latches and Flip-flops 2 Sequencing Static Circuits 3 2 Static Sequencing Element Methodology 4 Synchronizer 5 LECTURE 07: SEQUENTIAL