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ECAD and VLSI lab manual
ECAD & VLSI LAB MANUAL FOR B.TECH –ECE IV-1 SEMESTER BY SATHISH DADI M.TECH DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING www.jntuworld.com www.jntuworld.com www.jwjobs.net JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD IV Year B.Tech. ECE - I Sem L T/P/D C 0 -/3/- 2 E-CAD AND VLSI LAB List of Experiments Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects ( temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS) E-CAD programs: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools. 1. HDL code to realize all the logic gates 2. Design of 2-to-4 decoder 3. Design of 8-to-3 encoder (without and with parity) 4. Design of 8-to-1 multiplexer 5. Design of 4 bit binary to gray converter 6. Design of Multiplexer/ Demultiplexer, comparator 7. Design of Full adder using 3 modeling styles 8. Design of flip flops: SR, D, JK, T 9. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter 10. Finite State Machine Design www.jntuworld.com www.jntuworld.com www.jwjobs.net VLSI programs: 1. Introduction to layout design rules 2. Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following: Basic logic gates CMOS inverter CMOS NOR/ NAND gates CMOS XOR and MUX gates CMOS 1-bit full adder Static / Dynamic logic circuit (register cell) Latch Pass transistor 3. Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths 4. Introduction to SPICE simulation and coding of NMOS/CMOS circuit 5. SPICE simulation of basic analog circuits: Inverter / Differential amplifier 6. Analog Circuit simulation (AC analysis) – CS & CD amplifier 7. System level design using PLL Note: Any SIX of the above experiments from each part are to be conducted (Total 12) www.jntuworld.com www.jntuworld.com www.jwjobs.net EXPERIMENT -1 Simulation using all the modeling styles and Synthesis of all the logic gates usingVerilog HDL Aim: 1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in Verilog using a Test bench. 2. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: i) Xilinx Spartan 3E FPGA +CPLD Board ii) Model Sim simulation tool or Xilinx ISE Simulator tool iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to download onto FPGA). v) JTAG cable vi) Adator 5v/4A Boolean equations: And Gate:Y = (A.B) Or Gate: Y = (A + B) Nand Gate: Y = (A.B)’ Nor Gate: Y = (A+B)’ Xor Gate: Y = A.B’ + A’.B Xnor Gate: Y = A.B + A’.B’ www.jntuworld.com www.jntuworld.com www.jwjobs.net Block diagram: Verilog program for AND gate: // And Gate (In Dataflow, behavioral Modeling): Module andg(a,b,c); input a,b; output c; assign c = a & b; endmodule //behavioural modeling Module andg1(a,b,c); input a,b; always(a,b) begin if (a==1’b0 or b == 1’b0) c = 1’b0; else if (a==1’b0 or b == 1’b1) c = 1’b0; else if (a==1’b1 or b == 1’b0) c = 1’b0; else if (a==1’b1 or b == 1’b1) www.jntuworld.com www.jntuworld.com www.jwjobs.net c = 1’b1; endendmodule Verilog program for OR gate: //Or gate(Dataflow, behavioral modeling): Module org (a,b,c); input a,b; output c; assign c = a | b; endmodule Verilog program for nand gate: // Nand Gate (In Dataflow modeling): Module nandg (a,b,c); input a,b; output c; assign c = ~(a & b); endmodule Verilog program for NOR gate: // Nor Gate (In Dataflow modeling): Module norg (a,b,c); input a,b; output c; assign c = ~(a | b); endmodule www.jntuworld.com www.jntuworld.com www.jwjobs.net Verilog program for XOR gate: Xor gate(In Dataflow modeling): Module xorg (a,b,c); input a,b; output c; assign c = a ^ b; endmodule (or) Module xorg2 (a,b,c); input a,b; output c; assign c = (~a & b) | (a & ~b); endmodule Verilog program for XNOR gate: //Xnor Gate (In Dataflow modeling): Module xnorg (a,b,c); input a,b; output c; assign c = ~(a ^ b); endmodule www.jntuworld.com www.jntuworld.com www.jwjobs.net VHDL PROGRAM FOR ALL LOGIC GATES: library ieee; use ieee.std_logic_1164.all; entity digital_gates is port( x: in std_logic; y: in std_logic; sel:in std_logic_vector(1 downto 0); F: out std_logic); end digital_gates; architecture behav1 of digital_gates is begin process(x, y, sel) begin if (sel = "00") then F <= x and y; elsif (sel = "01") then F <= x or y; elsif (sel = "10") then F <= x nand y; elsif (sel = "11") then F <= x nor y; else F <= '0'; end if; end process; end behav1; www.jntuworld.com www.jntuworld.com www.jwjobs.net Test Bench: programmable digital gates library ieee; use ieee.std_logic_1164.all; entity tb_digital_gates is end tb_digital_gates; architecture behav1 of tb_digital_gates is component digital_gates is port( x: in std_logic; y: in std_logic; sel:in std_logic_vector(1 downto 0); F: out std_logic ); end component; signal x,y,F:std_logic; signal sel:std_logic_vector(1 downto 0); begin U1: digital_gates port map(x,y, sel,F); process begin x <= '0'; wait for 10 ns; x <= '1'; wait for 20 ns; end process; process begin y <= '0'; www.jntuworld.com www.jntuworld.com www.jwjobs.net wait for 20 ns; y <= '1'; wait for 30 ns; end process; process begin sel <= "00","01" after 20 ns,"10" after 40 ns,"11" after 80 ns; wait for 120 ns; end process; end behav1; www.jntuworld.com www.jntuworld.com www.jwjobs.net [...]... module decoder(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C); output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7; input A,B,C; wire s0,s1,s2; not (s0,A); not (s1,B); not (s2,C); and (Q0,s0,s1,s2); and (Q1,A,s1,s2); and (Q2,s0,B,s2); and (Q3,A,B,s2); and (Q4,s0,s1,C); and (Q5,A,s1,C); and (Q6,s0,B,C); and (Q7,A,B,C); endmodule //*****TESTBENCH*******// module stimulus; // Set up variables reg A, B, C; // Instantiate the decoder decoder FF(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C);... i2, i3; input s1, s0; // Internal wire declarations wire s1n, s0n; wire y0, y1, y2, y3; // Gate instantiations not (s1n, s1); not (s0n, s0); and (y0, i0, s1n, s0n); and (y1, i1, s1n, s0); and (y2, i2, s1, s0n); www.jntuworld.com www.jntuworld.com www.jwjobs.net and (y3, i3, s1, s0); or (out, y0, y1, y2, y3); endmodule /////TEST BENCH module stimulus; // Declare variables to be connected to inputs reg... circuit which performs the inverse of decoder.An encoder has 2^N input lines and N output lines.In encoder the output lines genrate the binary code corresponding to input value.The decimal to bcd encoder usually has 10 input lines and 4 ouput lines.The decoder decimal data as an input for decoder an encoded bcd ouput is available at 4 output lines www.jntuworld.com www.jntuworld.com www.jwjobs.net Y2... sel) if (sel == 1'b0) Y = A; else Y = B; endmodule ********************************** module mux2(out,i0,i1,s0); output out; input i0,i1,s0; //internal wires wire sbar,y1,y2; not g1(sbar,s0); and g2(y1,i0,sbar); and g3(y2,i1,s0); or g4(out,y1,y2); endmodule //test bench module text_mux2; reg i0,i1; reg s0; wire out; mux2 mymux(out,i0,i1,s0); initial $monitor($time,"s0=%b,i0=%b,i1=%b,out=%b\n",s0,i0,i1,out);... endmodule www.jntuworld.com www.jntuworld.com www.jwjobs.net EXPERIMENT -3 Design of 8-to-3 encoder (without and with parity) usingVerilog HDL - Aim: 1 Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in Verilog using a Test bench 2 Synthesize each one of them on two different EDA... == 1) begin for(k=0;k . (s0,A); not (s1,B); not (s2,C); and (Q0,s0,s1,s2); and (Q1,A,s1,s2); and (Q2,s0,B,s2); and (Q3,A,B,s2); and (Q4,s0,s1,C); and (Q5,A,s1,C); and (Q6,s0,B,C); and (Q7,A,B,C); endmodule //*****TESTBENCH*******//. UNIVERSITY HYDERABAD IV Year B.Tech. ECE - I Sem L T/P/D C 0 -/3/- 2 E-CAD AND VLSI LAB List of Experiments Design and implementation of the following CMOS digital/analog circuits using Cadence. program for AND gate: // And Gate (In Dataflow, behavioral Modeling): Module andg(a,b,c); input a,b; output c; assign c = a & b; endmodule //behavioural modeling Module andg1(a,b,c);