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2/1 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Course contents • Digital design Combinatorial circuits: without status • Sequential circuits: with status • FSMD design: hardwired processors • Language based HW design: VHDL 2/2 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Design of Combinatorial Circuits • Minimization of Boolean functions • Technology mapping • Correct timing behavior • Basic RTL building blocks (Adder, ALU, MUX, …) 2/3 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Design of Combinatorial Circuits • Minimization of Boolean functions Karnaugh map Minimization with the Karnaugh map Don’t care conditions Quine-McCluskey • Technology mapping • Correct timing behavior • Basic RTL building blocks (Adder, ALU, MUX, …) 2/4 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Design of Combinatorial Circuits • Minimization of Boolean functions Karnaugh map Minimization with the Karnaugh map Don’t care conditions Quine-McCluskey • Technology mapping • Correct timing behavior • Basic RTL building blocks (Adder, ALU, MUX, …) 2/5 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map • Motivation: Assume: F=xy’z+xy’z’ Cost = Σ(fan-in) complete circuit = (2)+(3)+(3)+(2) = 10 Delay Assume: relative gate delay NAND or NOR or NOT = 0.6 + fan-in * 0.4 Delay = Σ(gate-delay) critical path = 1 + (1.8+1) + (1.4+1) = 6.2 x y z F=xy’z+xy’z’ 2/6 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map • Motivation: F=xy’z+xy’z’ =xy’(z+z’) =xy’ The value of z hence does not matter Cost = Σ(fan-in) complete circuit = (1+2) = 3 i.o. 10 Delay Assume: relative gate delay NAND or NOR or NOT = 0.6 + fan-in * 0.4 Delay = Σ(gate-delay) critical path = 1 + (1.4+1) = 3.4 i.o. 6.2 x y z F 2/7 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map • Minimization via manipulation of Boolean expressions is clumsy: no method exists to select the theorems such that we are sure to obtain the minimum cost • Is it possible to see in the truth table which input value does not matter? x y z F 0 0 0 0 - 0 0 1 0 - 0 1 0 0 - 0 1 1 0 - 1 0 0 1 xy’z’ 1 0 1 1 xy’z 1 1 0 0 - 1 1 1 0 - We indeed see easily that the value of F equals 1 for x=1 and y=0 irrespective of the value of z We however see this easily only for z, since only for z the lines z=0 and z=1 for equal x and y are consecutive 2/8 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map • A Karnaugh map contains the same information as a truth table (each square is a minterm), but… • neighboring squares differ only in the value of 1 variable!! x’ x x 0 1 x’y’ x’y xy’ xy x 0 1 y 0 1 x’y’z’ x’y’z xy’z’ xy’z x 0 1 yz 00 01 x’yz x’yz’ xyz xyz’ 11 10 x y z x’z (y does not matter) x’y’z x’yz xy’z’ xyz’ xz’ (y does not matter) xy’z’ xy’z xy’ (z does not matter) 2/9 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map m 0 m 1 x 0 1 m 0 m 1 m 2 m 3 x 0 1 y 0 1 0 1 4 5 x 0 1 yz 00 01 3 2 7 6 11 10 x y z 2/10 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 Karnaugh map 0 1 4 5 xy 00 01 zw 00 01 3 2 7 6 11 10 x z w 12 13 8 9 15 14 11 10 11 10 y x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 Fill out from truth table [...]... 3 2 18 19 17 xy 16 00 01 Sequential circuits FSMD design w 4 5 7 6 22 23 21 20 01 11 12 13 15 14 30 31 29 28 11 10 8 9 11 10 26 27 25 24 10 F(v,x,y,z,w) Differs from course book 2/ 14 y x © R.Lauwereins Imec 20 01 Digital design Karnaugh map Differs from course book w zw xy 00 Combinatorial circuits z 00 01 z 11 10 10 11 01 00 y x 0 1 3 2 18 19 17 xy 16 00 4 5 7 6 22 23 21 20 01 11 12 13 15 14 30 31 29 ... wxyz wxyz Sequential circuits FSMD design VHDL Cost=4*1 +2* 3 +2* 2+1*4=18 Delay 2/ 22 Cost Delay =(1)+(.6+3*.4+1) +(.6+4*.4+1)=7 =4*1+1*3 +2* 2+1*3=14 =22 % cheaper =(1)+(.6+3*.4+1) +(.6+3*.4+1)=6.6 =6% faster © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 2/ 23 Minimization with the Karnaugh map • Example 2: F(v,w,x,y,z) v w x y z F v w x y z F 0 0 0 0 0 0... 23 21 20 01 11 12 13 15 14 30 31 29 28 11 10 8 9 11 10 26 27 25 24 10 VHDL y x F=(u,v,x,y,z,w) x y 2/ 15 w 01 Sequential circuits FSMD design v 10 40 41 43 42 58 59 57 56 10 11 44 45 47 46 62 63 61 60 11 01 36 37 39 38 54 55 53 52 01 00 32 33 35 50 51 49 48 00 34 x y u © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 2/ 16 Design of Combinatorial Circuits... 1 0 1 0 1 © R.Lauwereins Imec 20 01 Digital design Minimization with the Karnaugh map • Realisation as sum of 1-minterms: F=Σ (6,7,10,11,14,15 ,21 ,23 ,25 ,27 ,29 ,31) v w x y z Combinatorial circuits Sequential circuits FSMD design VHDL Cost=(5*1)+( 12* (5+1))+(1*( 12+ 1))=90 Delay=(.6+1*.4)+(.6+5*.4+1)+(.6+ 12* .4+1)=11 2/ 24 Minimization with the Karnaugh map © R.Lauwereins Imec 20 01 Digital design • Minimisation... = Delay = = 4*(1) + 7*(4) + 1*(7) 39 1 + (2. 2+1) + (3.4+1) 8.6 FSMD design VHDL 2/ 12 F © R.Lauwereins Imec 20 01 Digital design Karnaugh map Implement F=yw+xy’w’+y’z’w’ x y z w Combinatorial circuits F Sequential circuits FSMD design VHDL 2/ 13 Cost = = Delay = = 3*(1) + {1* (2) +2* (3)} + 1*(3) 14 i.p.v 39 1 + (1.8+1) + (1.8+1) 6.6 i.p.v 8.6 © R.Lauwereins Imec 20 01 Karnaugh map v Digital design w zw Combinatorial... =v’y(x+w)+vz(x+w) =(x+w)(v’y+vz) v w x y z Cost =(1*1)+(5* (2+ 1))=16 ( 82% cheaper) Delay =(.6+1*.4)+(.6 +2* .4+1) +(.6 +2* .4+1)+(.6 +2* .4+1) =8 .2 (25 % faster) Minimization with the Karnaugh map © R.Lauwereins Imec 20 01 Digital design • Dual minimisation Step 1: Create the Karnaugh map Combinatorial circuits v z z Sequential circuits y 0 VHDL x w 2/ 30 0 0 0 0 0 0 0 0 FSMD design 0 1 1 0 1 1 0 0 0 1 1 0 1... cheaper) Delay=(.6+1*.4)+(.6 +2* .4+1)+(.6+3*.4+1)=6 .2 (44% faster) 2/ 33 © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 2/ 34 Minimization with the Karnaugh map • Summary Realisation Sum of 1-minterms Minimal AND-OR 3-layers Minimal OR-AND Cost 90 22 16 14 Rel cost 100% 24 % 18% 16% Delay 11 7 8 .2 6 .2 Rel delay 100% 64% 75% 56% Area/time trade-off We’ll... circuits Minimization with the Karnaugh map • Realisation of F1min2=v’xy+v’wy+vxz+vwz v w x y z Sequential circuits FSMD design VHDL Cost=1+(4*(3+1))+(1*(4+1)) =22 (76% cheaper) Delay=(.6+1*.4)+(.6+3*.4+1)+(.6+4*.4+1)=7 (34% faster) 2/ 28 © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 2/ 29 Minimization with the Karnaugh map • Realisation in more than... VHDL x w 2/ 32 0 0 0 0 0 0 0 0 FSMD design 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 Is already the minimum coverage F0min2=(v+y)(w+x)(v’+z) © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Minimization with the Karnaugh map • Realisation of F0min2=(v+y)(w+x)(v’+z) v w x y z Sequential circuits FSMD design VHDL Cost=(1*1)+(3* (2+ 1))+(1*(3+1))=14 (84% cheaper) Delay=(.6+1*.4)+(.6 +2* .4+1)+(.6+3*.4+1)=6 .2. .. map Combinatorial circuits v z z Sequential circuits y 0 VHDL x w 2/ 25 0 0 0 0 0 0 0 0 FSMD design 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 Minimization with the Karnaugh map © R.Lauwereins Imec 20 01 Digital design • Minimisation Step 2: determine all prime implicants Combinatorial circuits v z z Sequential circuits y 0 VHDL x w 2/ 26 0 0 0 0 0 0 0 0 FSMD design 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 . 01 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 18 19 17 16 22 23 21 20 30 31 29 28 26 27 25 24 xy 11 10 10 11 01 00 00 01 11 10 x y z w x z w v y Differs from course book F(v,x,y,z,w) 2/ 15 © R.Lauwereins Imec. 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map 0 xy 00 01 zw 00 01 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 18 19 17 16 22 23 21 20 30 31 29 28 26 . 16 22 23 21 20 30 31 29 28 26 27 25 24 xy 11 10 10 11 01 00 00 01 11 10 x y z w x z w v y 40 41 43 42 44 45 47 46 36 37 39 38 32 33 35 34 58 59 57 56 62 63 61 60 54 55 53 52 50 51 49 48 10 11 01 00 x y 10 11 01 00 x y u F=(u,v,x,y,z,w) Differs