Part IV Data Path and Control Feb 2007 Computer Architecture, Data Path and Control Slide About This Presentation This presentation is intended to support the use of the textbook Computer Architecture: From Microprocessors to Supercomputers, Oxford University Press, 2005, ISBN 0-19-515455-X It is updated regularly by the author as part of his teaching of the upperdivision course ECE 154, Introduction to Computer Architecture, at the University of California, Santa Barbara Instructors can use these slides freely in classroom teaching and for other educational purposes Any other use is strictly prohibited © Behrooz Parhami Edition Released Revised Revised Revised Revised First July 2003 July 2004 July 2005 Mar 2006 Feb 2007 Feb 2007 Computer Architecture, Data Path and Control Slide A Few Words About Where We Are Headed Performance = / Execution time simplified to / CPU execution time CPU execution time = Instructions  CPI / (Clock rate) Performance = Clock rate / ( Instructions  CPI ) Try to achieve CPI = with clock that is as high as that for CPI > designs; is CPI < feasible? (Chap 15-16) Design memory & I/O structures to support ultrahigh-speed CPUs (chap 17-24)   Feb 2007 Define an instruction set; make it simple enough to require a small number of cycles and allow high clock rate, but not so simple that we need many instructions, even for very simple tasks (Chap 5-8) Computer Architecture, Data Path and Control Design hardware for CPI = 1; seek improvements with CPI > (Chap 13-14) Design ALU for arithmetic & logic ops (Chap 9-12) Slide IV Data Path and Control Design a simple computer (MicroMIPS) to learn about: • Data path – part of the CPU where data signals flow • Control unit – guides data signals through data path • Pipelining – a way of achieving greater performance Topics in This Part Chapter 13 Instruction Execution Steps Chapter 14 Control Unit Synthesis Chapter 15 Pipelined Data Paths Chapter 16 Pipeline Performance Limits Feb 2007 Computer Architecture, Data Path and Control Slide 13 Instruction Execution Steps A simple computer executes instructions one at a time • Fetches an instruction from the loc pointed to by PC • Interprets and executes the instruction, then repeats Topics in This Chapter 13.1 A Small Set of Instructions 13.2 The Instruction Execution Unit 13.3 A Single-Cycle Data Path 13.4 Branching and Jumping 13.5 Deriving the Control Signals 13.6 Performance of the Single-Cycle Design Feb 2007 Computer Architecture, Data Path and Control Slide 13.1 A Small Set of Instructions R I 31 op 25 rs 20 rt 15 rd 10 sh fn bits bits bits bits bits bits Opcode Source or base Source or dest’n Destination Unused Opcode ext J jta imm Operand / Offset, 16 bits Jump target address, 26 bits inst Instruction, 32 bits Fig 13.1 MicroMIPS instruction formats and naming of the various fields We will refer to this diagram later Seven R-format ALU instructions (add, sub, slt, and, or, xor, nor) Six I-format ALU instructions (lui, addi, slti, andi, ori, xori) Two I-format memory access instructions (lw, sw) Three I-format conditional branch instructions (bltz, beq, bne) Four unconditional jump instructions (j, jr, jal, syscall) Feb 2007 Computer Architecture, Data Path and Control Slide The MicroMIPS Instruction Set Copy Arithmetic Logic Memory access Control transfer Table 13.1 Feb 2007 Instruction Usage Load upper immediate Add  Subtract Set less than Add immediate  Set less than immediate AND OR XOR NOR AND immediate OR immediate XOR immediate Load word Store word Jump  Jump register Branch less than Branch equal Branch not equal  Jump and link System call  lui rt,imm add rd,rs,rt sub rd,rs,rt slt rd,rs,rt addi rt,rs,imm slti rd,rs,imm and rd,rs,rt or rd,rs,rt xor rd,rs,rt nor rd,rs,rt andi rt,rs,imm ori rt,rs,imm xori rt,rs,imm lw rt,imm(rs) sw rt,imm(rs) j L jr rs bltz rs,L beq rs,rt,L bne rs,rt,L jal L syscall Computer Architecture, Data Path and Control op fn 15 0 10 0 0 12 13 14 35 43 Slide 32 34 42 36 37 38 39 12 13.2 The Instruction Execution Unit beq,bne syscall R 31 I Next addr bltz,jr jta op 25 rs 20 10 sh fn 5 bits bits bits bits bits Opcode Source or base Source or dest’n Destination Unused Opcode ext J jta imm Operand / Offset, 16 bits Jump target address, 26 bits (rs) 12 A/L, lui, lw,sw ALU 22 instructions Address Data Data cache (rt) imm op fn Control Fig 13.2 Abstract view of the instruction execution unit for MicroMIPS For naming of instruction fields, see Fig 13.1 Feb 2007 inst Reg file inst rd Instruction, 32 bits rs,rt,rd Instr cache 15 bits j,jal PC rt Computer Architecture, Data Path and Control Slide 13.3 A Single-Cycle Data Path Incr PC Next addr jta Next PC (PC) PC Instr cache ALUOvfl rs rt inst rd 31 op (rs) Ovfl Reg file ALU (rt) / 16 imm Instruction fetch Fig 13.3 Feb 2007 ALU out Data addr Data cache Data out Data in Func 32 SE / 1 Register input fn RegDst Br&Jump Register writeback ALUSrc RegWrite Reg access / decode ALUFunc ALU operation DataRead RegInSrc DataWrite Data access Key elements of the single-cycle MicroMIPS data path Computer Architecture, Data Path and Control Slide ConstVar Shift function Constant amount Amount 5 Variable amount 00 01 10 11 No shift Logical left Logical right Arith right Shifter Function class 32 LSBs x Shifted y c0 32 Adder y 32 k / c 31 imm x y or MSB 32 c 32 An ALU for MicroMIPS lui 00 01 10 11 Shift Set less Arithmetic Logic 32 Shorthand symbol for ALU s Control x Func AddSub s ALU Logic unit AND OR XOR NOR 00 01 10 11 y 32input NOR Zero Ovfl Logic function Zero Ovfl Fig 10.19 A multifunction ALU with control signals (2 for function class, arithmetic, shift, logic) specifying the operation Feb 2007 Computer Architecture, Data Path and Control Slide 10