[...]... form of speed and power consumption, but suffers from a lack of mature high-level design tools In digital design, the industrial state of the art is register-transfer level (RTL) synthesis [IEE99, DC] This form of design involves explicitly specifying the cycle-by-cycle timing of the circuit and the word-length of each signal within the circuit The architecture must then be encoded using a mixture of. .. inputs and state-nodes S(z) = A(z)S(z) + B(z) (3.1) H(z) = C(z)S(z) + D(z) (3.2) The matrices C(z) and D(z) and are also matrices of polynomials in z −1 C(z) represents the z-domain relationship between state-node outputs and the outputs of all nodes D(z) represents the z-domain relationship between primary inputs and the outputs of all nodes It is clear that S(z) may be expressed as a matrix of rational... remainder of this section and turn to page 20 Given a computation graph G(V, S), let VI ⊂ V be the set of nodes of type inport, VO ⊂ V be the set of nodes of type outport, and VD ⊂ V be the set of nodes of type delay A matrix of transfer functions H(z) is required Matrix H(z) has elements hiv (z) for i ∈ VI and v ∈ V , representing the transfer function from primary input i to the output of node v... values, and simultaneously that overflow errors do not regularly occur, which would lead to low signal-to-noise ratio To determine an appropriate scaling, it is necessary to determine the peak value that each signal could reach Given a peak value P , a power -of- two scaling p is selected with p = log2 P + 1, since power -of- two multiplication is cost-free in a hardware implementation For some DSP algorithms, ... same word-length and scaling, although shift operations are often incorporated in fixed-point designs, in order to provide an element of scaling control [KKS98] Fig 2.4(c) shows a standard floating-point implementation, where the scaling of each signal is a function of time 2.5 Summary 13 A single uniform system word-length is common to both the traditional implementation styles This is a result of historical... representation of DSP algorithms using computation graphs 2.1 Digital Design for DSP Engineers 2.1.1 Microprocessors vs Digital Design One of the first options faced by the designer of a digital signal processing system is whether that system should be implemented in hardware or software A software implementation forms an attractive possibility, due to the mature state of compiler technology, and the number of. .. technology, and the number of good software engineers available In addition microprocessors are mass-produced devices and therefore tend to be reasonably inexpensive A major drawback of a microprocessor implementation of DSP algorithms is the computational throughput achievable Many DSP algorithms are highly parallelizable, and could benefit significantly from more fine-grain parallelism than that available... to the output of each of these state nodes The transfer functions from each input to each state node output may be expressed as in (3.1), where A, and B are matrices of polynomials in z −1 Each of these matrices represents a z-domain relationship once the feedback has been broken at the outputs of state-nodes A(z) represents the transfer function between statenodes and state-nodes, and B(z) represents... the severity of overflow-induced errors This is exploited by the proposed combined word-length and scaling optimization algorithm in order to automate the design of saturation arithmetic systems Chapter 6 addresses the implications of the proposed multiple word-length scheme for the problem of architectural synthesis The chapter starts by highlighting the differences between architectural synthesis for... raise the level of abstraction at which a DSP algorithm can be specified for hardware synthesis We shall argue that, often, the most efficient hardware implementation of an algorithm is one in which a wide variety of finite precision representations of different sizes are used for different internal variables The size of the representation of a finite precision ‘word’ is referred to as its word-length Implementations . DSP algorithms is the computational throughput achievable. Many DSP algorithms are highly parallelizable, and could benefit significantly from more fine-grain parallelism than that available with gen- eral.