Digital Logic and Microprocessor Design With VHDL Enoch O. Hwang La Sierra University, Riverside  %URRNV&ROH ,6%1  ſ7HDP(/(&7521L; To my wife and children, Windy, Jonathan and Michelle Contents Contents  Preface  Chapter 1 Designing Microprocessors  1.1 Overview of a Microprocessor  1.2 Design Abstraction Levels  1.3 Examples of a 2-to-1 Multiplexer  1.3.1 Behavioral Level  1.3.2 Gate Level  1.3.3 Transistor Level  1.4 Introduction to VHDL  1.5 Synthesis  1.6 Going Forward  1.7 Summary Checklist  1.8 Problems   Chapter 2 Digital Circuits 2 2.1 Binary Numbers 3 2.2 Binary Switch  2.3 Basic Logic Operators and Logic Expressions  2.4 Truth Tables  2.5 Boolean Algebra and Boolean Function  2.5.1 Boolean Algebra  2.5.2 * Duality Principle  2.5.3 Boolean Function and the Inverse  2.6 Minterms and Maxterms  2.6.1 Minterms  2.6.2 * Maxterms  2.7 Canonical, Standard, and non-Standard Forms  2.8 Logic Gates and Circuit Diagrams  2.9 Example: Designing a Car Security System  2.10 VHDL for Digital Circuits  2.10.1 VHDL code for a 2-input NAND gate  2.10.2 VHDL code for a 3-input NOR gate  2.10.3 VHDL code for a function  2.11 Summary Checklist  2.12 Problems   Chapter 3 Combinational Circuits  3.1 Analysis of Combinational Circuits  3.1.1 Using a Truth Table  3.1.2 Using a Boolean Function  3.2 Synthesis of Combinational Circuits  3.3 * Technology Mapping  3.4 Minimization of Combinational Circuits  3.4.1 Karnaugh Maps  3.4.2 Don’t-cares  3.4.3 * Tabulation Method  3.5 * Timing Hazards and Glitches  5 3.5.1 Using Glitches  3.6 BCD to 7-Segment Decoder  3.7 VHDL for Combinational Circuits  3.7.1 Structural BCD to 7-Segment Decoder  3.7.2 Dataflow BCD to 7-Segment Decoder  3.7.3 Behavioral BCD to 7-Segment Decoder  3.8 Summary Checklist  3.9 Problems   Chapter 4 Standard Combinational Components  4.1 Signal Naming Conventions  4.2 Adder  4.2.1 Full Adder  4.2.2 Ripple-carry Adder  4.2.3 * Carry-lookahead Adder  4.3 Two’s Complement Binary Numbers  4.4 Subtractor  4.5 Adder-Subtractor Combination  4.6 Arithmetic Logic Unit  4.7 Decoder  4.8 Encoder  4.8.1 * Priority Encoder  4.9 Multiplexer  4.9.1 * Using Multiplexers to Implement a Function  4.10 Tri-state Buffer  4.11 Comparator  4.12 Shifter  4.12.1 * Barrel Shifter  4.13 * Multiplier  4.14 Summary Checklist  4.15 Problems   Chapter 5 * Implementation Technologies  5.1 Physical Abstraction  5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)  5.3 CMOS Logic  5.4 CMOS Circuits  5.4.1 CMOS Inverter  5.4.2 CMOS NAND gate  5.4.3 CMOS AND gate  5.4.4 CMOS NOR and OR Gates  1 5.4.5 Transmission Gate  5.4.6 2-input Multiplexer CMOS Circuit 1 5.4.7 CMOS XOR and XNOR Gates 1 5.5 Analysis of CMOS Circuits . 1 5.6 Using ROMs to Implement a Function . 15 5.7 Using PLAs to Implement a Function  1 5.8 Using PALs to Implement a Function 1 5.9 Complex Programmable Logic Device (CPLD)  5.10 Field Programmable Gate Array (FPGA)  5.11 Summary Checklist  5.12 Problems  6 Chapter 6 Latches and Flip-Flops  6.1 Bistable Element  6.2 SR Latch  6.3 SR Latch with Enable  6.4 D Latch  6.5 D Latch with Enable  6.6 Clock  6.7 D Flip-Flop . 1 6.7.1 * Alternative Smaller Circuit  1 6.8 D Flip-Flop with Enable  1 6.9 Asynchronous Inputs  1 6.10 Description of a Flip-Flop  6.10.1 Characteristic Table  1 6.10.2 Characteristic Equation  1 6.10.3 State Diagram  1 6.10.4 Excitation Table  1 6.11 Timing Issues  1 6.12 Example: Car Security System – Version 2  6.13 VHDL for Latches and Flip-Flops  1 6.13.1 Implied Memory Element  1 6.13.2 VHDL Code for a D Latch with Enable  6.13.3 VHDL Code for a D Flip-Flop . 19 6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear  6.14 * Flip-Flop Types  6.14.1 SR Flip-Flop  6.14.2 JK Flip-Flop  6.14.3 T Flip-Flop  6.15 Summary Checklist  6.16 Problems   Chapter 7 Sequential Circuits 2 7.1 Finite-State-Machine (FSM) Models  7.2 State Diagrams  7.3 Analysis of Sequential Circuits  7.3.1 Excitation Equation  7.3.2 Next-state Equation  7.3.3 Next-state Table  7.3.4 Output Equation  7.3.5 Output Table  7.3.6 State Diagram .0 7.3.7 Example: Analysis of a Moore FSM  7.3.8 Example: Analysis of a Mealy FSM  7.4 Synthesis of Sequential Circuits  7.4.1 State Diagram  7.4.2 Next-state Table  7.4.3 Implementation Table  7.4.4 Excitation Equation and Next-state Circuit  7.4.5 Output Table and Equation . 1 7.4.6 FSM Circuit  7.4.7 Examples: Synthesis of Moore FSMs  7.4.8 Example: Synthesis of a Mealy FSM  7.5 Unused State Encodings and the Encoding of States  7.6 Example: Car Security System – Version 3  7.7 VHDL for Sequential Circuits  7 7.8 * Optimization for Sequential Circuits  7.8.1 State Reduction . 3 7.8.2 State Encoding  7.8.3 Choice of Flip-Flops  7.9 Summary Checklist  7.10 Problems   Chapter 8 Standard Sequential Components 2 8.1 Registers  8.2 Shift Registers  8.2.1 Serial-to-Parallel Shift Register  8.2.2 Serial-to-Parallel and Parallel-to-Serial Shift Register  8.3 Counters  8.3.1 Binary Up Counter  8.3.2 Binary Up-Down Counter  8.3.3 Binary Up-Down Counter with Parallel Load  8.3.4 BCD Up Counter  8.3.5 BCD Up-Down Counter  8.4 Register Files  8.5 Static Random Access Memory  2 8.6 * Larger Memories  8.6.1 More Memory Locations  2 8.6.2 Wider Bit Width  2 8.7 Summary Checklist  2 8.8 Problems  2  Chapter 9 Datapaths 2 9.1 Designing Dedicated Datapaths  9.1.1 Selecting Registers  9.1.2 Selecting Functional Units  9.1.3 Data Transfer Methods  9.1.4 Generating Status Signals  9.2 Using Dedicated Datapaths  9.3 Examples of Dedicated Datapaths  9.3.1 Simple IF-THEN-ELSE  9.3.2 Counting 1 to 10  9.3.3 Summation of n down to 1  9.3.4 Factorial  9.3.5 Count Zero-One  9.4 General Datapaths  9.5 Using General Datapaths  9.6 A More Complex General Datapath  9.7 Timing Issues  9.8 VHDL for Datapaths  9.8.1 Dedicated Datapath  9.8.2 General Datapath  9.9 Summary Checklist  9.10 Problems   Chapter 10 Control Units  10.1 Constructing the Control Unit  10.2 Examples  8 10.2.1 Count 1 to 10  10.2.2 Summation of 1 to n  10.3 Generating Status Signals  10.4 Timing Issues  10.5 Standalone Controllers  10.5.1 Rotating Lights  10.5.2 PS/2 Keyboard Controller  10.5.3 VGA Monitor Controller 6 10.6 * ASM Charts and State Action Tables . 37 10.6.1 ASM Charts 37 10.6.2 State Action Tables 0 10.7 VHDL for Control Units 1 10.8 Summary Checklist 2 10.9 Problems 4  Chapter 11 Dedicated Microprocessors  11.1 Manual Construction of a Dedicated Microprocessor  11.2 Examples  11.2.1 Greatest Common Divisor  11.2.2 Summing Input Numbers  11.2.3 High-Low Guessing Game  11.2.4 Finding Largest Number  11.3 VHDL for Dedicated Microprocessors  11.3.1 FSM + D Model  11.3.2 FSMD Model  11.3.3 Behavioral Model  11.4 Summary Checklist  11.5 Problems   Chapter 12 General-Purpose Microprocessors  12.1 Overview of the CPU Design  12.2 The EC-1 General-Purpose Microprocessor  12.2.1 Instruction Set  12.2.2 Datapath 5 12.2.3 Control Unit  12.2.4 Complete Circuit  12.2.5 Sample Program 0 12.2.6 Simulation  12.2.7 Hardware Implementation 2 12.3 The EC-2 General-Purpose Microprocessor 3 12.3.1 Instruction Set  12.3.2 Datapath 4 12.3.3 Control Unit 5 12.3.4 Complete Circuit 8 12.3.5 Sample Program 9 12.3.6 Hardware Implementation 1 12.4 VHDL for General-Purpose Microprocessors 2 12.4.1 Structural FSM+D 2 12.4.2 Behavioral FSMD 9 12.5 Summary Checklist 2 12.6 Problems 2 9 Appendix A Schematic Entry Tutorial 1  A.1 Getting Started  A.1.1 Preparing a Folder for the Project  A.1.2 Starting MAX+plus II  A.1.3 Starting the Graphic Editor  A.2 Using the Graphic Editor 4 A.2.1 Drawing Tools 4 A.2.2 Inserting Logic Symbols 4 A.2.3 Selecting, Moving, Copying, and Deleting Logic Symbols  A.2.4 Making and Naming Connections 6 A.2.5 Selecting, Moving and Deleting Connection Lines  A.3 Specifying the Top-Level File and Project  A.3.1 Saving the Schematic Drawing  A.3.2 Specifying the Project  A.4 Synthesis for Functional Simulation  A.5 Circuit Simulation  A.5.1 Selecting Input Test Signals  A.5.2 Customizing the Waveform Editor  A.5.3 Assigning Values to the Input Signals  A.5.4 Saving the Waveform File  A.5.5 Starting the Simulator  A.6 Creating and Using the Logic Symbol   Appendix B VHDL Entry Tutorial 2  B.1 Getting Started  B.1.1 Preparing a Folder for the Project  B.1.2 Starting MAX+plus II  B.1.3 Creating a Project  B.1.4 Editing the VHDL Source Code  B.2 Synthesis for Functional Simulation  B.3 Circuit Simulation  B.3.1 Selecting Input Test Signals  B.3.2 Customizing the Waveform Editor  B.3.3 Assigning Values to the Input Signals  B.3.4 Saving the Waveform File  B.3.5 Starting the Simulator   Appendix C UP2 Programming Tutorial 3  C.1 Getting Started  C.1.1 Preparing a Folder for the Project  C.1.2 Creating a Project  C.1.3 Viewing the Source File  C.2 Synthesis for Programming the PLD  C.3 Circuit Simulation  C.4 Using the Floorplan Editor  C.4.1 Selecting the Target Device  C.4.2 Maping the I/O Pins with the Floorplan Editor  C.5 Fitting the Netlist and Pins to the PLD  C.6 Hardware Setup  C.6.1 Installing the ByteBlaster Driver  C.6.2 Jumper Settings  C.6.3 Hardware Connections  C.7 Programming the PLD  C.8 Testing the Hardware  C.9 MAX7000S EPM7128SLC84-7 Summary  10 C.9.1 JTAG Jumper Settings  C.9.2 Prototyping Resources for Use  C.9.3 General Pin Assignments  C.9.4 Two Pushbutton Switches  C.9.5 16 DIP Switches  C.9.6 16 LEDs  C.9.7 7-Segment LEDs  C.9.8 Clock  C.10 FLEX10K EPF10K70RC240-4 Summary  C.10.1 JTAG Jumper Settings  C.10.2 Prototyping Resources for Use  C.10.3 Two Pushbutton Switches  C.10.4 8 DIP Switches  C.10.5 7-Segment LEDs  C.10.6 Clock  C.10.7 PS/2 Port  C.10.8 VGA Port   Appendix D VHDL Summary  D.1 Basic Language Elements  D.1.1 Comments  D.1.2 Identifiers  D.1.3 Data Objects  D.1.4 Data Types  D.1.5 Data Operators  D.1.6 ENTITY  D.1.7 ARCHITECTURE  D.1.8 GENERIC  D.1.9 PACKAGE  D.2 Dataflow Model Concurrent Statements  D.2.1 Concurrent Signal Assignment 0 D.2.2 Conditional Signal Assignment  D.2.3 Selected Signal Assignment  D.2.4 Dataflow Model Example 2 D.3 Behavioral Model Sequential Statements  D.3.1 PROCESS  D.3.2 Sequential Signal Assignment  D.3.3 Variable Assignment  D.3.4 WAIT  D.3.5 IF THEN ELSE  D.3.6 CASE 4 D.3.7 NULL  D.3.8 FOR  D.3.9 WHILE  D.3.10 LOOP  D.3.11 EXIT  D.3.12 NEXT  D.3.13 FUNCTION  D.3.14 PROCEDURE  D.3.15 Behavioral Model Example  D.4 Structural Model Statements  D.4.1 COMPONENT Declaration  D.4.2 PORT MAP  D.4.3 OPEN  D.4.4 GENERATE  D.4.5 Structural Model Example  11 [...]... ieee.std _logic_ 1164.ALL; ENTITY and2 gate IS PORT( i1, i2: IN STD _LOGIC; 24 y Digital Logic and Microprocessor Design with VHDL Chapter 1 - Designing Microprocessors o: OUT STD _LOGIC) ; END and2 gate; ARCHITECTURE Dataflow OF and2 gate IS BEGIN o . output, and storage devices. Rather, Digital Logic and Microprocessor Design with VHDL Chapter 1 - Designing Microprocessors 17 the focus is on the design. faculty and students. Enoch O. Hwang Riverside, California Digital Logic and Microprocessor Design with VHDL Preface 15 Chapter 1 Designing Microprocessors