194 Appendix B: Verilog Code for Schematics in Chapter 5 // SIGNAL DECLARATIONS wire clk; wire data; wire enable; reg out; // ASSIGN STATEMENTS // MAIN CODE // Clocked condition always @(posedge clk) begin if (enable) out <= data; end endmodule // eff Listing B.7 Figure 5.13 (Continued) Listing B.8 Figure 5.9 /*********************************************************/ // MODULE: glitch // // FILE NAME: glitch.v // VERSION: 1.0 // DATE: June 1, 2002 // AUTHOR: Bob Zeidman, Zeidman Consulting // // CODE TYPE: RTL // // DESCRIPTION: This module defines a mux circuit with a // potential glitch. // /*********************************************************/ // DEFINES Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Listing B.8: Figure 5.9 195 // TOP MODULE module glitch( d0, d1, sel, z); // PARAMETERS // INPUTS input d0; // data input input d1; // data input input sel; // select // OUTPUTS output z; // output // INOUTS // SIGNAL DECLARATIONS wire d0; wire d1; wire sel; wire z; // ASSIGN STATEMENTS assign z = sel ? d1 : d0; // MAIN CODE endmodule // glitch Listing B.8 Figure 5.9 (Continued) Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. 196 Appendix B: Verilog Code for Schematics in Chapter 5 Listing B.9 Figure 5.10 /*********************************************************/ // MODULE: no glitch // // FILE NAME: no_glitch.v // VERSION: 1.0 // DATE: June 1, 2002 // AUTHOR: Bob Zeidman, Zeidman Consulting // // CODE TYPE: RTL // // DESCRIPTION: This module defines a mux circuit without a // potential glitch. // /*********************************************************/ // DEFINES // TOP MODULE module no_glitch( clk, d0, d1, sel, z); // PARAMETERS // INPUTS input clk; // system clock input d0; // data input input d1; // data input input sel; // select // OUTPUTS output z; // output Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Listing B.10: Figure 5.11 197 // INOUTS // SIGNAL DECLARATIONS wire d0; wire d1; wire sel; wire zp; // intermediate signal reg z; // ASSIGN STATEMENTS assign zp = sel ? d1 : d0; // MAIN CODE // Clocked condition always @(posedge clk) z <= zp; endmodule // no_glitch Listing B.9 Figure 5.10 (Continued) Listing B.10 Figure 5.11 /*********************************************************/ // MODULE: gated clock // // FILE NAME: gated.v // VERSION: 1.0 // DATE: June 1, 2002 // AUTHOR: Bob Zeidman, Zeidman Consulting // // CODE TYPE: RTL // // DESCRIPTION: This module defines a circuit with a gated // clock. // Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. 198 Appendix B: Verilog Code for Schematics in Chapter 5 /*********************************************************/ // DEFINES // TOP MODULE module gated( clk, data, gate, out); // PARAMETERS // INPUTS input clk; // system clock input data; // data input input gate; // gate input // OUTPUTS output out; // output // INOUTS // SIGNAL DECLARATIONS wire clk; wire data; wire gate; wire gclk; // gated clock reg out; // ASSIGN STATEMENTS assign gclk = gate & clk; // MAIN CODE Listing B.10 Figure 5.11 (Continued) Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Listing B.11: Figure 5.12 199 // Clocked condition always @(posedge gclk) out <= data; endmodule // gated Listing B.10 Figure 5.11 (Continued) Listing B.11 Figure 5.12 /*********************************************************/ // MODULE: not gated clock // // FILE NAME: not_gated.v // VERSION: 1.0 // DATE: June 1, 2002 // AUTHOR: Bob Zeidman, Zeidman Consulting // // CODE TYPE: RTL // // DESCRIPTION: This module defines a circuit without a // gated clock. This is an enable flip-flop. // /*********************************************************/ // DEFINES // TOP MODULE module not_gated( clk, data, gate, out); // PARAMETERS // INPUTS input clk; // system clock Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. 200 Appendix B: Verilog Code for Schematics in Chapter 5 input data; // data input input gate; // gate input // OUTPUTS output out; // output // INOUTS // SIGNAL DECLARATIONS wire clk; wire data; wire gate; wire mux; // mux output reg out; // ASSIGN STATEMENTS assign mux = gate ? data : out; // MAIN CODE // Clocked condition always @(posedge gclk) out <= mux; endmodule // not_gated Listing B.11 Figure 5.12 (Continued) Listing B.12 Figure 5.15 /*********************************************************/ // MODULE: potentially metastable circuit // // FILE NAME: meta.v // VERSION: 1.0 // DATE: June 1, 2002 // AUTHOR: Bob Zeidman, Zeidman Consulting // Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Listing B.12: Figure 5.15 201 // CODE TYPE: RTL // // DESCRIPTION: This module defines a circuit that can // potentially go metastable due to an asynchronous input. // /*********************************************************/ // DEFINES // TOP MODULE module meta( clk, async_in, out1, out2); // PARAMETERS // INPUTS input clk; // system clock input async_in; // asynchronous input // OUTPUTS output out1; // output 1 output out2; // output 2 // INOUTS // SIGNAL DECLARATIONS wire clk; wire async_in; reg in; // intermediate signal reg out1; reg out2; Listing B.12 Figure 5.15 (Continued) Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. 202 Appendix B: Verilog Code for Schematics in Chapter 5 // ASSIGN STATEMENTS // MAIN CODE // Clocked condition always @(posedge gclk) begin in <= async_in; out1 <= in; out2 <= in; end endmodule // meta Listing B.12 Figure 5.15 (Continued) Listing B.13 Figure 5.16 /*********************************************************/ // MODULE: less metastable circuit // // FILE NAME: less_meta.v // VERSION: 1.0 // DATE: June 1, 2002 // AUTHOR: Bob Zeidman, Zeidman Consulting // // CODE TYPE: RTL // // DESCRIPTION: This module defines a circuit that can still // potentially go metastable due to an asynchronous input. // It uses a synchronizing flip-flop to lessen the chance // of metastability. // /*********************************************************/ // DEFINES // TOP MODULE Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Listing B.13: Figure 5.16 203 module less_meta( clk, async_in, out1, out2); // PARAMETERS // INPUTS input clk; // system clock input async_in; // asynchronous input // OUTPUTS output out1; // output 1 output out2; // output 2 // INOUTS // SIGNAL DECLARATIONS wire clk; wire async_in; reg sync_in; // synchronized input reg in; // intermediate signal reg out1; reg out2; // ASSIGN STATEMENTS // MAIN CODE // Clocked condition always @(posedge clk) begin sync_in <= async_in; in <= sync_in; out1 <= in; Listing B.13 Figure 5.16 (Continued) Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. [...]... purchase PDF Split-Merge on www.verypdf.com to remove this watermark Let’s compare your choices GO BACK TO SCHOOL TAKE A CHALKBOARD COURSE Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark Math Toolkit for Real-Time Programming by Jack W Crenshaw Develop a solid understanding of the math behind common functions — and learn how to make your programs run faster and more... Engineers as IEEE-STD-1364 VHDL — A standard hardware description language, maintained by the Institute of Electrical and Electronic Engineers as IEEE-STD-1076 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark References Logic Design Manual for ASICs Santa Clara, CA: LSI Logic Corporation, 1989 Davenport Jr., Wilbur B Probability and Random Processes New York, NY: McGraw-Hill... physics and electrical engineering at Cornell University and a master's degree in electrical engineering at Stanford University Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark Index Numerics 10/10 rule 112–113, 129 4-bit numbers 75 A ABEL 5, 7, 205 ABEL program 7 Actel Corporation Designer® 157 algorithmic model 75 Altera Corporation 143, 155, 167 ALU 34, 89, 151 AND 97, 104 AND. .. Boolean equation that are ANDed together PROM — Programmable read only memory can be easily programmed with specific contents Once programmed, the data cannot be erased pseudorandom — This refers to a sequence of numbers that are predictable and repeatable, but are produced in such a way that they have the same characteristics and distribution as numbers that are selected randomly race condition — A... equations and does not have any reliance on timing or sequencing DeMorgan's Law — A law of Boolean Algebra that states that A & B = ~(~A | ~B) and that A | B = ~(~A & ~B) It was named after the nineteenth century mathematician Augustus De Morgan who discovered it Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark Glossary DFT — Design for test — This is the practice of designing. .. designed integrated circuits and circuit boards and has written software for many different types of systems As a consultant, his clients have included Apple Computer, Cisco Systems, Ikos Systems and Texas Instruments Among his publications are technical papers on hardware and software design methods as well as two textbooks — Verilog Designer’s Library published by Prentice-Hall and Introduction to Verilog... changes voltage Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark Glossary SOPC — System on a programmable chip — this term is used to describe a very complex and very dense programmable device, a CPLD or FPGA, that can contain so much logic that it can be considered an entire system SRAM — Static random access memory is memory that can be written and read numerous times while... first and the lower Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark 212 Glossary level implementation details are filled in later TTL — Transistor-transistor logic — a common type of circuit for implementing logic functions in which the output is driven by two BJT transistors Verilog — A standard hardware description language, maintained by the Institute of Electrical and. .. purchase PDF Split-Merge on www.verypdf.com to remove this watermark 213 214 References About the Author Bob Zeidman is the president of Zeidman Consulting (www.ZeidmanConsulting.com), an EDA firm offering tools for simulating, prototyping, and emulating network devices He is also the founder and president of The Chalkboard Network (www.chalknet.com), which provides seminars and courses on high tech topics... programmable device while it is soldered in a system and the system is powered up SRAM-based devices can be programmed in-system EPROM-, EEPROM-, and Flash PROM–based devices can be programmed in-system if the device includes the pins and internal circuitry to support this feature IP — Intellectual property — the parts of a chip design that are considered unique and are protected by patent laws Usually this . circuit with a // potential glitch. // /*********************************************************/ // DEFINES Please purchase PDF Split-Merge on www.verypdf.com. DESCRIPTION: This module defines a circuit with a gated // clock. // Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. 198 Appendix