... SD -16(R1),F12 SD -40 (R1),F 24 ADDD F 24, F22,F2 SD - 24( R1),F16 SD -32(R1),F20 ADDD F8,F6,F2 ADDD F16,F 14, F2 ADDD F20,F18,F2 SD 0(R1),F4 ADDD F4,F0,F2 ADDD F12,F10,F2 LD F26, -48 (R1) SD 8(R1),F28 ... unrolling and scheduling work on a superscalar version of DLX with the delays in clock cycles from Figure 4. 2 on page 2 24 4. 4 EXAMPLE Below is the loop we unrolled and scheduled earlier in section 4. 1 ... i+1: Iteration i+2: LD ADDD SD LD ADDD SD LD ADDD SD F0,0(R1) F4,F0,F2 0(R1),F4 F0,0(R1) F4,F0,F2 0(R1),F4 F0,0(R1) F4,F0,F2 0(R1),F4 The selected instructions are then put together in the loop...