... operation of combina-
tional circuits.
• Design BCD-to-seven-segment and hexadecimal-to-seven-segment de-
coders, including special features such as ripple blanking, using VHDL and
Graphic Design Files ... the
Application
155
❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚
❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚...
... Function
74HC00A High-speed CMOS Quad 2-input NAND
74HC02 High-speed CMOS Quad 2-input NOR
74ALS04 Advanced low-power Schottky TTL Hex inverter
74LS11 Low-power Schottky TTL Triple 3-input AND
74F20 FAST ... transform any gate from an AND- shaped to an OR-
shaped gate and vice versa.
Digital signal (or pulse waveform) A series of 0s and 1s plot-
ted over time.
Distinctive-shape symbo...
... Time R
S
=
0Ω (
Figure 5
)12 .5 s
From ALE
t
H1
,t
H0
OE Control to Q Logic State C
L
=
50 pF, R
L
=
10k (
Figure 8
) 1 25
25 50 ns
25 50 ns
250 ns
t
1H
,t
0H
OE Control to Hi-Z C
L
=
10 pF, R
L
=
10k ... classes of circuits. An analog-to -digital con-
verter accepts an analog voltage or current at its input and produces a corresponding digi-
tal code. A digital- to-analog conve...
... 1/64
ϭ 45/ 64
ϭ 0.7031 25
10
❘❙❚
Fractional-Decimal-to-Fractional-Binary Conversion
Simple decimal fractions such as 0 .5, 0. 25, and 0.3 75 can be converted to binary fractions
by a sum-of-powers ... decimal numbers to binary. Use the
sum-of-powers-of-2 method for parts a, c, e, and g. Use
the repeated-division-by-2 method for parts b, d, f, and h.
a. 75
10
e. 63
10
b. 83
10
f. 64
1...
... and
POS Networks in
Figure 3. 35
ABC Y
000 1
001 0
010 0
011 1
100 1
101 0
110 0
111 0
FIGURE 3. 35
Unsimplified SOP and POS Networks
The sum-of-products and product-of-sums expressions represented ... one cell of the circled pair, and B is a coordinate of the other. (Dis-
card B/B
ෆ
.)
Y ϭ A
ෆ
Three- and Four-Variable Maps
Refer to the forms of three- and four-variable Karnaugh...
... process used by CPLD design software to inter-
pret design information (such as a drawing or text file) and cre-
ate required programming information for a CPLD.
Complex PLD (CPLD) A digital device ... interpreted by design software to generate programming in-
formation for the CPLD.
Compile The process used by CPLD design software to interpret design informa-
tion (such...
... Write Ϫ16
10
a. As an 8-bit 2’s complement number
b. As a 5- bit 2’s complement number
(8-bit numbers are more common than 5- bit numbers in digital systems, but it is use-
ful to see how we must ... the 16’s complement of
EA54. Try it.
❘❙❚ EXAMPLE 6.16 Subtract 8B63 Ϫ 55 D7 using the complement method.
SOLUTION Find the 16’s complement of 55 D7.
FFFF
Ϫ 55 D7
AA28 ( 15 s complement)
ϩ...
... 358 CHAPTER 8 • Introduction to Programmable Logic Architectures
Carry-In and
Cascade-In
Carry-Out and
Cascade-Out
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE8
Dedicated Inputs and
Global ... thus permanently enabling the output buffers.
The fuses numbered 256 5 and 256 7 select the polarity at pins ( 15) and (17). Fuse
256 5 is blown. The fused input to the corresponding XOR gate float...
... modulus is 5.
The timing diagram and state diagram are shown in Figure 9.12. Since this circuit pro-
duces one pulse on Q
2
for every 5 clock pulses, we can use it as a divide-by -5 circuit.
366 CHAPTER ... Flip-Flop)
INPUT
RESET
INPUT
VCC
CLOCK
Q
3
OUTPUT
element
Q
COUNT
CLOCK
RESET
Q
2
OUTPUT
element
Q
COUNT
CLOCK
RESET
Q
1
OUTPUT
element
Q
COUNT
CLOCK
RESET
Q
0
OUTPUT
element
Q
CO...