... www.ti.comDon'tDoAnalogPowerPlaneUnwantedCapacitanceDigitalPowerPlaneUSBPHYLayoutGuideFigure7.DoNotCrossPlaneBoundariesãDonotoverlapplanesthatdonotreferenceeachother.Forexample,donotoverlapadigitalpowerplanewithananalogpowerplaneasthisproducesacapacitancebetweentheoverlappingareasthatcouldpassRFemissionsfromoneplanetotheother,asshowninFigure8.Figure8.DoNotOverlapPlanesSPRAAR7December200 7USB2 .0BoardDesignandLayoutGuidelines7SubmitDocumentationFeedback www.ti.com2USBPHYLayoutGuide2.1GeneralRoutingandPlacement2.2SpecificGuidelinesforUSBPHYLayout2.2.1Analog,PLL,andDigitalPowerSupplyFilteringAnalogPowerSupplySoCBoardFerriteBeadDigitalPowerSupplyFerriteBead0.1àF0.01àF0.001àF10àF0.1àF0.01àF0.001àF10àFUSBPHYLayoutGuideThefollowingsectionsdescribeindetailthespecificguidelinesforUSBPHYLayout.UsethefollowingroutingandplacementguidelineswhenlayingoutanewdesignfortheUSBphysicallayer(PHY).Theseguidelineshelpminimizesignalqualityandelectromagneticinterference(EMI)problemsonafour-or-morelayerevaluationmodule(EVM).ãPlacetheUSBPHYandmajorcomponentsontheun-routedboardfirst.Formoredetails,seeSection2.2.3.ãRoutethehigh-speedclockandhigh-speedUSBdifferentialsignalswithminimumtracelengths.ãRoutethehigh-speedUSBsignalsontheplaneclosesttothegroundplane,wheneverpossible.ãRoutethehigh-speedUSBsignalsusingaminimumofviasandcorners.Thisreducessignalreflectionsandimpedancechanges.ãWhenitbecomesnecessarytoturn90,usetwo45turnsoranarcinsteadofmakingasingle90turn.Thisreducesreflectionsonthesignaltracesbyminimizingimpedancediscontinuities.ãDonotrouteUSBtracesunderornearcrystals,oscillators,clocksignalgenerators,switchingregulators,mountingholes,magneticdevicesorICsthatuseorduplicateclocksignals.ãAvoidstubsonthehigh-speedUSBsignalsbecausetheycausesignalreflections.Ifastubisunavoidable,thenthestubshouldbelessthan200mils.ãRouteallhigh-speedUSBsignaltracesovercontinuousplanes(VCCorGND),withnointerruptions.Avoidcrossingoveranti-etch,commonlyfoundwithplanesplits.ThefollowingsectionsdescribeindetailthespecificguidelinesforUSBPHYLayout.TominimizeEMIemissions,adddecouplingcapacitorswithaferritebeadatpowersupplyterminalsfortheanalog,phase-lockedloop(PLL),anddigitalportionsofthechip.Placethisarrayasclosetothechipaspossibletominimizetheinductanceofthelineandnoisecontributionstothesystem.AnanaloganddigitalsupplyexampleisshowninFigure1.Incaseofmultiplepowersupplypinswiththesamefunction,tiethemuptoasinglelow-impedancepointintheboardandthenaddthedecouplingcapacitors,inadditiontotheferritebead.ThisarrayofcapsandferritebeadimproveEMIandjitterperformance.TakebothEMIandjitterintoaccountbeforealteringtheconfiguration.Figure1.SuggestedArrayCapacitorsandaFerriteBeadtoMinimizeEMI 2USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7December2007SubmitDocumentationFeedback ... 1BackgroundApplicationReportSPRAAR7–December2007 USB2 .0BoardDesignandLayoutGuidelinesDSPSApplications ABSTRACTThisdocumentdiscussesschematicguidelineswhendesigningauniversalserialbus (USB) system.Contents1Background 12USBPHYLayoutGuide ... www.ti.com3.4ESDProtectionSystemDesignConsideration4ReferencesReferencesESDprotectionsystemdesignconsiderationiscoveredinSection2ofthisdocument.ThefollowingareadditionalconsiderationsforESDprotectioninasystem.ãMetallicshieldingforbothESDandEMIãChassisGNDisolationfromtheboardGNDãAirgapdesignedonboardtoabsorbESDenergyãClampingdiodestoabsorbESDenergyãCapacitorstodivertESDenergyãTheuseofexternalESDcomponentsontheDP/DMlinesmayaffectsignalqualityandarenotrecommended. USB2 .0Specification,Intel,2000,http://www .usb. org/developers/docs/ãHighSpeedUSBPlatformDesignGuidelines,Intel,2000,http://www.intel.com/technology /usb/ download /usb2 dg_R1_0.pdfãSelectionandSpecificationofCrystalsforTexasInstrumentsUSB2.0Devices(SLLA122)1 0USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7December2007SubmitDocumentationFeedback...