... number of frames containing memories from 65 to 16. Sharing framesamong RMs also allows frame caching, which minimizesICAP accesses by reading and writing a shared frame onlyonce during a series ... readsthe outputs of the RMs and writes their inputs, a processcalled s oftware connectivity. On the other hand, hardwareconnectivity is the joining of RM outputs to RM inputsdirectly in the FPGA. ... mapping of the RTLcode to the hardware prior to simulation, and that mappingremains static. Since many processes are idle, and since activ-ity can change during simulation prior, static mapping...