... on x
n
k
. So eventually B(x
n
k
,
1
n
k
) is inside G
i
0
, contradictory to
18
Topology Course Lecture Notes
Aisling McCluskey and Brian McMaster
August 1997
their choice! (More rigorously, there ... sequence is just a function having the positive integers as do-
main. The set of positive integers, of course, possesses a particularly simple
ordering; there is a first member, second me...
... KHOA
KHOA ĐIỆN-ĐIỆN TỬ
BỘ MÔN KỸ THUẬT ĐIỆN TỬ
1
1
VLSI DESIGN
Thiết kế vi mạch số
Chapter 0: Course Introduction
Bộ môn Kỹ Thuật Điện Tử
Course Information
• Instructor
– Truong Quang Vinh, ... http://www4.hcmut.edu.vn/~tqvinh
– Office: 116B1, IC Design Lab, Monday 9-11am
2
Bộ môn Kỹ Thuật Điện Tử
Textbooks
1. Neil Weste and David Harris, CMOS VLSI Design A Circuits and System...
... 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
CMOS VLSI Design
4th Ed.
0: Introduction 12
0
V
DD
A Y
GND
CMOS Inverter
A Y
0 1
1 0
A Y
OFF
ON
1
ON
OFF
CMOS VLSI Design
4th Ed.
0: Introduction 13
CMOS ... OFF
ON
OFF
1
0
ON ON
OFF
OFF
0
0
A
B
Y
CMOS VLSI Design
4th Ed.
0: Introduction 14
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
B
Y
CMOS VLSI Design
4th Ed.
0: Introducti...
... Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 6
nMOS Cutoff
No channel
I
ds
≈ 0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
CMOS VLSI DesignCMOS VLSI Design
4th ... C
g
for contacted diff
– ½ C
g
for uncontacted
– Varies with process
Lecture 3:
CMOS
Transistor
Theory
CMOS VLSI DesignCMOS VLSI...
... ox
2q
2q
A
A
N
t
N
C
ε
γε
ε
= =
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 16
Body Effect Cont.
For small source-to-body voltage, treat as linear
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: ... L
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 19
Leakage
What about current in cutoff?
Simulated results
What differs...
... inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
d = 6RC
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 28
Delay Model Comparison
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response ... −
V
out
(t)
V
in
(t)
t
0
t
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)
Lecture 5:
DC &
Transient
Response
CMOS VLSI DesignCMOS VLSI D...
...
activity factor
– Depends on design, but typically α ≈ 0.1
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
7: Power 15
Switching Probability
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
7: Power 16
Example
... V
DD
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
7: Power 27
NAND3 Leakage Example
100 nm process
I
gn
= 6.3 nA I
gp
= 0
I
offn
= 5.63 nA I
offp
= 9.3 nA
Data from [Lee03]...