... Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 6
nMOS Cutoff
No channel
I
ds
≈ 0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
CMOS VLSI DesignCMOS VLSI ... µ
p
= 2
-5 -4 -3
-2 -1 0
-0 .8
-0 .6
-0 .4
-0 .2
0
I
ds
(mA)
V
gs
= -5
V
gs
= -4
V
gs...
... 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
CMOS VLSI Design
4th Ed.
0: Introduction 12
0
V
DD
A Y
GND
CMOS Inverter
A Y
0 1
1 0
A Y
OFF
ON
1
ON
OFF
CMOS VLSI Design
4th Ed.
0: Introduction 13
CMOS NAND Gate
A B Y
0 ... OFF
ON
OFF
1
0
ON ON
OFF
OFF
0
0
A
B
Y
CMOS VLSI Design
4th Ed.
0: Introduction 14
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
B
Y
CMOS VLSI...
... ox
2q
2q
A
A
N
t
N
C
ε
γε
ε
= =
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 16
Body Effect Cont.
For small source-to-body voltage, treat as linear
CMOS VLSI DesignCMOS VLSI Design
4th ... [Song01]
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 23
Junction Leakage
Reverse-biased p-n junctions have some leakage
–...
... = 6RC
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 28
Delay Model Comparison
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 29
Example: 3-input ... as long as you are consistent
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 27
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverte...
... outline
1
Stern-Gerlach and the discovery of spin
2
Spinors, spin operators, and Pauli matrices
3
Spin precession in a magnetic field
4
Paramagnetic resonance and NMR
Background: expectations pre-Stern-Gerlach
Previously, ... of additional oscillating resonant in-plane magnetic field
B
1
(t) for a time, t, such that
ω
1
t =
π
2
,ω
1
= γB
1
(“π/2 pulse”) orients majority spin in xy-plane where i...
... 10
16
-1 0
18
cm
-3
less highly doped regions
generally labeled n/p
(without the +)
P
P
+
+
-
group V
element
ion
electro
n
n-type Donor
free
carrier
B
B
+
+
-
group III
element
hole
p-type ... V
GS
-Vtn
ECE 410, Prof. A. Mason Lecture Notes 6.18
nMOS Current vs.Voltage
• Saturation Region (Active Region)
–V
GS
> Vtn, V
DS
> V
GS
-Vtn
• surface potential at drain, φ
s...
... delay for n-input R-C adder
t
n
= t
d
(a
0
,b
0
⇒ c
1
) + (n-2) t
d
(c
in
⇒ c
out
) + t
d
(c
in
⇒ s
n-1
)
first stage delay: inputs to carry-out
middle stage (n-2) delay: carry-in to carry-out
last ... 410, Prof. A. Mason Lecture Notes 12.11
Ripple-Carry Adders in CMOS
• Simple to implement and connect for multi-bit addition
– but, they are very slow
• Worse-case delays in R-C Adders
– ea...