... Therefore, when Clk = 1, and if D = 0, then n3 (which is equal to D) will be 0; thus asserting R' and resetting the output latch Q to 0. On the other hand, when Clk = 1, and ... the two inputs to the NAND gate, E and R, are 1 and 0 respectively. With S' asserted and R' de-Chapter 6 – Latches and Flip-Flops Page 16 of 28 Digital Logic and Microprocessor Design ... circuits, on the other hand, change states only at the active edge of the clock signal. Asynchronous inputs are usually available for both flip-flops and latches, and they are used to either set or...