Digital Integrated Circuits Jan M Rabaey A Design Perspective Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 © Digital Integrated Circuits2nd Memories Chapter Overview  Memory Classification  Memory Architectures  The Memory Core  Periphery  Reliability  Case Studies © Digital Integrated Circuits2nd Memories Semiconductor Memory Classification Read-Write Memory Random Access Non-Random Access SRAM FIFO DRAM Non-Volatile Read-Write Memory EPROM E PROM Read-Only Memory Mask-Programmed Programmable (PROM) FLASH LIFO Shift Register CAM © Digital Integrated Circuits2nd Memories Memory Timing: Definitions Read cycle READ Read access Read access Write cycle WRITE Write access Data valid DATA Data written © Digital Integrated Circuits2nd Memories Memory Architecture: Decoders M bits S0 S1 S2 SN2 SN2 M bits S0 Word Word Word Storage cell Word A0 Word A1 Word Storage cell AK WordN2 WordN2 WordN2 WordN2 K log N Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals © Digital Integrated Circuits2nd Input-Output (M bits) Decoder reduces the number of select signals K = log2N Memories Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH AK AK1 AL Bit line Row Decoder 2L K Word line M.2K Sense amplifiers / Drivers A0 AK2 Column decoder Amplify swing to rail-to-rail amplitude Selects appropriate word Input-Output (M bits) © Digital Integrated Circuits2nd Memories Hierarchical Memory Architecture Block Block i Block P Row address Column address Block address Global data bus Control circuitry Block selector Global amplifier/driver I/O Advantages: Shorter wires within blocks Block address activates only block => power savings © Digital Integrated Circuits2nd Memories Block Diagram of Mbit SRAM Clock generator Z-address buffer X-address buffer Predecoder and block selector Bit line load Transfer gate Column decoder Sense amplifier and write driver CS, WE buffer © Digital Integrated Circuits2nd I/O buffer x1/x4 controller Y-address buffer [Hirose90] X-address buffer Memories Contents-Addressable Memory Commands Comparand © Digital Integrated Circuits2nd CAM Array words3 64 bits Priority Encoder Control Logic R/W Address (9 bits) Address Decoder Mask Validity Bits I/O Bufers Data (64 bits) Memories Memory Timing: Approaches Address bus Row Address Column Address RAS Address Bus Address Address transition initiates memory operation CAS RAS-CAS timing DRAM Timing Multiplexed Adressing © Digital Integrated Circuits2nd SRAM Timing Self-timed Memories Programmable Logic Array Pseudo-NMOS PLA GND GND GND V DD GND GND GND GND V DD X0 X0 X1 AND-plane © Digital Integrated Circuits2nd X1 X2 X2 f0 f1 OR-plane Memories Dynamic PLA f AND V DD GND f OR f OR f AND V DD X0 X0 X1 X1 AND-plane © Digital Integrated Circuits2nd X2 X2 f0 f1 GND OR-plane Memories Clock Signal Generation for self-timed dynamic PLA f f f AND Dummy AND row f AND tpre teval f AND f OR Dummy AND row f OR (a) Clock signals © Digital Integrated Circuits2nd (b) Timing generation circuitry Memories PLA Layout And-Plane VDD x0 x0 x1 x1 x2 x2 Pull-up devices © Digital Integrated Circuits2nd Or-Plane φ GND f0 f1 Pull-up devices Memories Mbit SRAM Hierarchical Word-line Architecture Global word line Sub-global word line Local word line Block group select Block select ••• Local word line ••• ••• Memory cell Block © Digital Integrated Circuits2nd Block Block select Block Memories Bit-line Circuitry Block select Bit-line load ATD BEQ Local WL Memory cell B/T B/T CD CD CD I/O line Sense amplifier © Digital Integrated Circuits2nd I/O I/O Memories Sense Amplifier (and Waveforms) Address I /O I /O ATD SEQ Block select ATD BEQ BS SA BS Vdd I/O Lines GND SA SEQ SEQ SEQ SEQ SEQ Vdd DATA Dei SA, SA GND DATA BS Data-cut © Digital Integrated Circuits2nd Memories Gbit Flash Memory BL16996 BL16897BL33791 ··· SGD WL31 WL0 SGS Block0 Block1023 BLT0 BLT1 Data Caches (10 24 32)3 © Digital Integrated Circuits2nd Block1023 Bit Line Control Circuit Sense Latches (10 24 32)3 I/O Block0 Word Line Driver BL0 BL1 ·····BL16895 Word Line Driver Word Line Driver 512Mb Memory Array Word Line Driver 512Mb Memory Array Sense Latches (1024 32)3 Data Caches (1024 32)3 From [Nakamura02] Memories Number of memory cells Writing Flash Memory Verify level 0.8 V Word-line level 4.5 V 5 108 106 104 102 Result of times program 0V 1V 2V 3V 4V Vt of memory cells (a) 1V 2V 3V 4V Vt of memory cells Evolution of thresholds © Digital Integrated Circuits2nd 100 0V Final Distribution From [Nakamura02] Memories Charge pump 2kB Page buffer & cache 10.7mm 125mm2 1Gbit NAND Flash Memory 32 word lines x 1024 blocks 16896 bit lines 11.7mm © Digital Integrated Circuits2nd From [Nakamura02] Memories 125mm2 1Gbit NAND Flash Memory                   Technology Technology 0.13µm p-sub CMOS triple-well 0.13µm p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al 1poly, 1polycide, 1W, 2Al Cell size 0.077µm2 Cell size 0.077µm2 Chip size 125.2mm2 Chip size 125.2mm2 Organization 2112 x 8b x 64 page x 1k block Organization 2112 x 8b x 64 page x 1k block Power supply 2.7V-3.6V Power supply 2.7V-3.6V Cycle time 50ns Cycle time 50ns Read time 　 25µs Read time 　 25µs Program time 200µs //page Program time 200µs page Erase time 2ms // block Erase time 2ms block © Digital Integrated Circuits2nd From [Nakamura02] Memories Semiconductor Memory Trends (up to the 90’s) Memory Size as a function of time: x every three years © Digital Integrated Circuits2nd Memories Semiconductor Memory Trends (updated) © Digital Integrated Circuits2nd From [Itoh01] Memories Trends in Memory Cell Area © Digital Integrated Circuits2nd From [Itoh01] Memories Semiconductor Memory Trends Technology feature size for different SRAM generations © Digital Integrated Circuits2nd Memories ... Circuits2nd Source line contact Courtesy Toshiba Memories Characteristics of State-of-the-art NVM © Digital Integrated Circuits2nd Memories Read-Write Memories (RAM)  STATIC (SRAM) Data stored as... Q= VDD BL = Memories CMOS SRAM Analysis (Write) © Digital Integrated Circuits2nd Memories 6T-SRAM — Layout VDD M2 M4 Q Q M1 M3 GND M5 BL © Digital Integrated Circuits2nd M6 WL BL Memories Resistance-load... Circuits2nd SRAM Timing Self-timed Memories Read-Only Memory Cells BL BL BL VDD WL WL WL BL WL BL WL BL WL GND Diode ROM © Digital Integrated Circuits2nd MOS ROM MOS ROM Memories MOS OR ROM BL[0] BL[1]