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Systems Design and Programming Basic I/O I CMPE 3101 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Basic I/O InstructionsWe discussed IN, OUT, INS and OUTS as instructions for the transfer of datato and from an I/O device.IN and OUT transfer data between an I/O device and the microprocessor’saccumulator (AL, AX or EAX).The I/O address is stored in:• Register DX as a 16-bit I/O address (variable addressing).• The byte, p8, immediately following the opcode (fixed address).Only 16-bits (A0 to A15) are decoded.Address connections above A15 are undefined for I/O instructions.0000H-03XXH are used for the ISA bus.INS and OUTS transfer to I/O devices using ES:DI and DS:SI, respectively.IN AL, 19H;8-bits are saved to AL from I/O port 19H.IN EAX, DX;32-bits are saved to EAX.OUT DX, EAX;32-bits are written to port DX from EAX.OUT 19H, AX;16-bits are written to I/O port 0019H. Systems Design and Programming Basic I/O I CMPE 3102 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Isolated versus Memory-Mapped I/OIsolated and Memory-Mapped I/O: In the Isolated scheme, IN, OUT, INS and OUTS are required. In the Memory-mapped scheme, any instruction that references memorycan be used.8-bit port addresses used to access system board device, e.g. timer and key-board.16-bit port addresses used to access serial and parallel ports, harddrives, etc.00000FFFFFMemory1M X 80000FFFF64K X 8I/OI/O64K X 8Separate spacesOverlappedHardware using M/IO andW/R needed to developsignalsIORC and IOWC.Requires IN, OUT, INS andOUTSIORC and IOWC not required.Any data transfer instruction.A portion of the memory spaceis used for I/O devices.spacesDisadvantage:Advantage:Disadvantage: Systems Design and Programming Basic I/O I CMPE 3103 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6I/O Map0000I/O Expansion Area DMA controllerInterrupt controllerTimer8255(PPI)COM 2Hard diskLPT 1CGI adapterFloppy diskCOM 1FFFF00100020004000240060004402F80064032003000378033003D0038003F003E003F8Fixed I/O areas0400Fixed PortI/O instuctionsVariable PortI/O instuctionsComputer systemand ISA BusPCI Bus, user appsand main-boardfunctions Systems Design and Programming Basic I/O I CMPE 3104 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Basic I/O InterfaceThe basic input device (to the microprocessor) is a set of tri-state buffers.The basic output device (from the microprocessor) is a set of latches.Basic Input Interface:VCCData BusSEL1A11A21A31A42A12A22A32A41Y11Y21Y31Y42Y12Y22Y32Y41G2G74ALS24410KΩWhen tri-states are enabled,Toggle switchesare data source.8-bit input portmicroprocessor can readstate of toggle switches intoAL (using IN instruction).I/O port address decoded to SEL Systems Design and Programming Basic I/O I CMPE 3105 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Basic I/O InterfaceBasic Output Interface:In this case, the data from the OUT instruction is latched usingSEL.SELData BusVCC330ΩD0D1D2D3D4D5D6D7Q0Q1Q2Q3Q4Q5Q6Q7OCCLKU1D flip-flops holdLight-emittingdiodes emit74ALS374data from microprocessorwhen Q outputis set to logic 0. Systems Design and Programming Basic I/O I CMPE 3106 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6HandshakingI/O devices are typically slower than the microprocessor.Handshaking is used to synchronize I/O with the microprocessor.A device indicates that it is ready for a command or data (through someI/O pin or port).The processor issues a command to the device, and the device indicatesit is busy (not ready).The I/O device fi nishes its task and indicates a ready condition, and thecycle continues.There are two basic mechanisms for the processor to service a device.Polling: Processor initiated. Device indicates it is ready by setting some sta-tus bit and the processor periodically checks it. Interrupts: Device initiated. The act of setting a status bit causes an inter-rupt, and the processor calls an ISR to service the device. Systems Design and Programming Basic I/O I CMPE 3107 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6HandshakingA printer connected to the parallel port requires handshaking.The parallel port specifi cation is shown below:The processor writes ASCII data out to the Datax pins of the printer andtoggles the Data Strobe pin to latch it in.The printer raises the Busy pin.When the Busy pin goes low, the sequence repeats.13121110987625242322212019185432117161514DB25DB25 CENT36 Function DB25 CENT36 Function1 1 Data Strobe 12 12 Paper out2 2 Data0 13 13 Select3 3 Data1 14 14 Afd4 4 Data2 15 32 Error5 5 Data3 16 - RESET6 6 Data4 17 31 Select in7 7 Data5 18-25 19-30 GND8 8 Data6 - 17 Frame GND9 9 Data7 - 16 GND10 10 Ack - 33 GND11 11 Busy192021222324252627282930313233343536123456789101112131415161718CENT36 Systems Design and Programming Basic I/O I CMPE 3108 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Interfacing CircuitryThe terminal characteristics of the processor must be matched to those of theI/O devices.Input Devices:They are either: TTL (0.0V-0.8V low and 2.0-5.0V high) or compatible. Switch-based; usually either open or connected.These must be conditioned before they can be used properly.For example, to make a simple (single-pole, single-throw) toggleswitch TTL compatible:2.2kΩVCCTTL OutputSPSTThis ensures thatthe output is heldat either 0 or logic 1at all times (it neverfloats).The value of R can varybetween 1K and 10KΩ. Systems Design and Programming Basic I/O I CMPE 3109 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Interfacing CircuitryInput Devices:Mechanical switches physically bounce when they are closed (causingthem to momentarily open after being closed).This can cause a problem if they are used as a clocking signal.Two asynchronous flip-flop solutions ar e given below:The basic idea is that these flip-flops stor e the values even if the D/Dnodes both float.VCC1kΩDDVCC1kΩQQDD74LS0474LS04A BQQ74LS0074LS00Cross-coupled NANDs.More practical inverterimplementation. Systems Design and Programming Basic I/O I CMPE 31010 (April 1, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Interfacing CircuitryOutput Devices:Interfacing an output device requires matching the voltage and currentrelationships of the devices and processor.Remember that the standard output levels of TTL compatible devices are0.0 to 0.4V for logic 0 and 2.4V to 5.0V for logic 1.The current levels are 0.0 to 2.0mA (logic 0) and 0.0 to -400uA (logic1).For example:VCC330Ω2N2222InputLight Emitting Diode18KMicroprocessorRequires 10mA of currentto light.Assume ~2.0V falls across theR1 = 3.0V/10mA = ~300Ω2N2222 has gain of ~100.Base current should be0.1mA.With a minimum high of2.4V and a 0.7V BE drop,1.7V falls across the R2.diode and supply is 5V.R2R1R2 = 1.7V/0.1mA = ~17K. [...]... (April 1, 2002) For the 64-bit data buses of the Pentium, the I/O ports can appear in any of the 8 banks However, only 32-bit transfers are supported, as there are no 64-bit transfer instructions 32-bit ports are becoming more popular because of PCI bus primarily The EISA and VESA local bus are also 32-bit buses YLAND BA L U M B C AR CMPE 310 Input devices can be 8-bit or 16-bit Note that instead of... O2 O3 O4 O5 O6 O7 O8 16L8 D7 -D0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 UMBC Note that only an 8-bit I/O port address is decoded BHE IOWC A0 A1 A2 A3 A4 A5 A6 A7 D15-D8 12 D0 Q0 Q1 Q2 Q3 D7 Q4 Q5 OC Q6 CLK Q7 74LS374 D0 Q0 Q1 Q2 Q3 D7 Q4 Q5 OC Q6 CLK Q7 74LS374 (April 1, 2002) Port 40H Two separate 8-bit output devices Port 41H I/O Port Decoding Similar to memory writes, any 8-bit I/O write request requires... 8086 through the 80386SX are also set up like the memory The text gives examples of 8-bit decoding and 16-bit decoding, which is a straightforward application of devices we’ve used for memory decoding For isolated I/O, IORC and IOWC are developed using M/IO and W/R pins of the microprocessor I/O Port Decoding For memory-mapped I/O, decoding is identical to memory decoding Systems Design and Programming... buses YLAND BA L U M B C AR CMPE 310 Input devices can be 8-bit or 16-bit Note that instead of latches, high impedance buffers (74ALS244) are used in these cases I/O Port Decoding Output devices can be 16-bit in which case BHE is not needed Systems Design and Programming MO UN TI RE COUNT Y . 32 Error5 5 Data3 16 - RESET6 6 Data4 17 31 Select in7 7 Data5 1 8-2 5 1 9-3 0 GND8 8 Data6 - 17 Frame GND9 9 Data7 - 16 GND10 10 Ack - 33 GND11 11 Busy192021222324252627282930313233343536123456789101112131415161718CENT36 Systems. 8086 through the 80386SX are also set up like the mem-ory.FFFFFFFD00030001D1 5-- D8FFFEFFFC00020000D 7-- D0High bankBHE BLE (A0)FFFB0005Low bankFFFA0004 Systems