Place & Route

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Place & Route

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CHAPTER 16 Place and Route This chapter discusses the process of implementing the synthesis netlist of the CPU design into a target FPGA device. The place and route tools read the netlist, extract the components and nets from the netlist, place the compo- nents on the target device, and interconnect the components using the specified interconnections. After the place and route process is complete, the designer has an imple- mentation of the design in the target technology. The im- plementation still needs to be verified for logical and tim- ing correctness. 16 Chapter Sixteen 370 Place and Route Process The place and route process places each macro from the synthesis netlist into an available location on the target silicon and connects the macros using routing resources available on the target silicon. The place and route process is shown in Figure 16-1. The synthesis netlist is input to the placement process. The placement process analyzes all of the macros used in the design and their connectivity to try to determine an optimal placement for the macros. The placement algorithms take into account a number of technology-specific factors of the target technology to determine whether a particular placement is good or not. After a trial placement and signal route is attempted, the design is analyzed with respect to timing constraints. If the timing constraints are not met, the place and route software continues to try different placements and signal routing to try to meet the constraints. Typical target devices have areas of the chip where logical functions are placed, and areas where interconnect signals are routed to connect the logical functions. This is shown in Figure 16-2. The device is split into a number of logic areas with routing channels that surround the logic areas. Logic areas contain the logical gates to implement the boolean function of the design. Routing channels contain the signals that are used to connect the logical gates together. For FPGA devices, the routing channels contain programmable interconnect wires. FPGA devices use an onboard RAM to store the value of programmable switches that are used to form the signal interconnections. By enabling the proper sets of pass transistor gates, signal interconnections between logic gates can be formed as shown in the example in Figure 16-3. To make a connection from logic block 1 to logic block 3, all of the switches shown need to be enabled with a logic 1 value. The logic gates of the devices are connected to local routing signals that can be connected to more global routing signals by pass transistors that bridge the two signals. The control signals of the pass transistors are stored in a loadable Constraints Met? Synthesis Netlist Placement Routing Yes No Figure 16-1 Place and Route Process. 371 Place and Route RAM. The place and route tool generates the RAM image to be loaded into the RAM on the device. The routing channels contain vertical and horizontal lines. The hori- zontal wires connect devices within a row, while the vertical lines allow connections across rows. Most routing channels contain wires of different Logic Block 1 Logic Block 2 Logic Block 3 1 1 1 1 Figure 16-3 Logic Block Interconnection. Logic Area Logic Area Logic Area Logic Area Logic Area Logic Area Logic Area Logic Area Logic Area Routing Channels Figure 16-2 FPGA Chip Architecture. lengths that allow connections to adjacent logic areas. Sometimes, longer connections are needed, and either a longer line must be used or shorter lines must be connected together to form the connection. This is shown in Figure 16-4. The job of the place and route tool is to create the programming files that will be used to specify the logic function of the logic macros in the logic areas and the switch programming of the wires used to connect the macros together. Too many switches on a routed signal can cause some negative performance effects. Each switch adds capacitance and resistance to the routed signal. After only a few connections, signals start to slow signifi- cantly because of the capacitance and resistance of the line. The place and route tool, therefore, must try to minimize long connections and the number of switches for a particular signal to create designs with the highest speed. To get the highest utilization, the place and route tools need to pack as many of the logical functions into a logic area as possible and then use as much local routing resources as possible to connect these functions. The place and route tools can make tradeoffs if the speed-critical signals are known ahead of time and are implemented using the highest speed interconnect signals. The placement algorithm also tries to place logical gates on the critical path close to each other so that local interconnect can be used to connect the gates. Local interconnect is usually very fast because the wires are short. Short wires have less capacitance and resistance and, therefore, can operate at much higher speeds. Chapter Sixteen 372 1 10 2 11 9 18 8 17 3 12 13 4 14 5 15 6 7 Connects short segments together Figure 16-4 Vertical and Horizon- tal Routing. Placing and Routing the Device The target device for the CPU design, as mentioned in earlier chapters, is an FPGA device. The device used is the Apex 20KE architecture from Altera. The place and route tools used with the Apex 20KE architecture are in the Quartus toolset. Quartus is a set of tools that includes not only place and route, but VHDL entry, VHDL simulation, gate-level simulation, and timing analysis. The first step in the process is to compile the design into the place and route environment. Setting Up a Project Most tools that work on a design with multiple data descriptions have a project manager to keep all of the files for that design in one place. This facilitates file management of the design. The first step in the place and route process is to set up a project. In the case of the Quartus environment, the project is usually named the same as the output EDIF file from syn- thesis. The Quartus user interface is shown in Figure 16-5. Selecting the File Project Wizard menu item will bring up a wizard that walks the user through the creation of a new project. The first pane 373 Place and Route Figure 16-5 Quartus User Interface. of this wizard is shown in Figure 16-6. This introduces the concept of a wizard to the user. The next step is to select the directory that contains the EDIF file that was generated by Leonardo Spectrum. In Figure 16-7, the directory of the EDIF file, the name of the project, and the name of the top-level entity are specified. It is usually a good idea to make the name of the project and top-level entity the same. The next step in the wizard is to add the EDIF file to the project. Clicking the next button brings up the interface shown in Figure 16-8. Using the button with the three dots, the file user can find the file and add it to the project. The next step is to specify the EDA settings so that the EDIF file can be properly interpreted. Use the Project EDA Tool Settings menu item to invoke the EDA Tool Settings Dialog box shown in Figure 16-9. The Design entry/synthesis tool item needs to be changed to Leonardo Spectrum. The next step is to select the physical device to implement. Remember we will use the EP20K200EFC484 device. This device is selected from the list of devices shown in Figure 16-10. The Chips and Devices tab displays a list of devices to select from. The list includes the device and the speed grade. Finally the device pins need to be assigned to the ports of the VHDL design. The cpu clock port must be assigned to a pad driver that is capable Chapter Sixteen 374 Figure 16-6 New Project Wizard. 375 Place and Route Figure 16-8 Specify Project Input File. Figure 16-7 New Project Settings. Chapter Sixteen 376 Figure 16-9 EDA Tool Settings Dialog Box Figure 16-10 Specify Target Device. of driving all the flip flops in the design. This requires a clock buffer rather than a standard buffer. In Figure 16-11 the clock port is assigned to a dedicated clock buffer port. Now that all the parameters have been specified, the place and route process can be run by selecting the Processing Start Compilation menu item. After the compilation process completes, the results are displayed (see Figure 16-12). SUMMARY In this chapter, the netlist output from the synthesis tool was read by the place and route tool, and an implementation of the netlist was generated. We examined the process required to run the place and route tool, the inputs to the place and route tool, and the outputs from it. In the next chapter, we examine how to verify that the design created from the place and route tool meets our requirements. 377 Place and Route Figure 16-11 Specify Pin Assignments. Chapter Sixteen 378 Figure 16-12 Results after Compilation. . Constraints Met? Synthesis Netlist Placement Routing Yes No Figure 16-1 Place and Route Process. 371 Place and Route RAM. The place and route tool generates the. and tim- ing correctness. 16 Chapter Sixteen 370 Place and Route Process The place and route process places each macro from the synthesis netlist into

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