CHAPTER 13 Basic Synthesis Concepts CPU: Description This chapter answers the question, “What are abstract data types?” The idea of using well-designed abstract data types (ADTs) to simplify the development life cycle and to create reusable code is well established This chapter covers the baIn this chapter, we further refine the CPU description and sics of designing and implementing ADTs in an object-oriexamine the RTL (Register Transfer Level) description of ented programming language As a foundation to exploring the CPU The CPU is described by a number of lower-level data abstraction, we will take a look inside Java and excomponents that are instantiated to form the CPU design plore some of the internal workings of the Java runtime sysAt the top of the CPU design is an architecture that tem Java reference objects will be explained The passing instantiates all of the lower-level components to form of reference and value types as arguments and how each the CPU The CPU block diagram is shown in Figure 13-1 type of argument passing is used in the Java programming language will be discussed Near the end of this chapter, exercises are provided to stimulate understanding in the use of reference objects 304 Figure 13-1 CPU Block Diagram Chapter Thirteen OpRegsel OpReg Reg0 Instrsel InstrReg Reg1 Reg2 Alusel Reg3 • Compsel Comp ALU Regsel Compout • Shifter Shiftsel Reg7 OutReg Clock Outsel Reset ProgCnt Control Progsel Addrsel AddrReg Addr(15:0) Data(15:0) Ready R/W VMA Following is an implementation of this block diagram, shown by file cpu.vhd: library IEEE; use IEEE.std_logic_1164.all; use work.cpu_lib.all; entity cpu is port(clock, reset, ready : in std_logic; port(addr : out bit16; port(rw, vma : out std_logic; port(data : inout bit16); end cpu; architecture rtl of cpu is component regarray port( data : in bit16; port( sel : in t_reg; port( en : in std_logic; port( clk : in std_logic; port( q : out bit16); end component; CPU: Synthesis Description component reg port( a : in bit16; port( clk : in std_logic; port( q : out bit16); end component; component trireg port( a : in bit16; port( en : in std_logic; port( clk : in std_logic; port( q : out bit16); end component; component control port( clock : in std_logic; port( reset : in std_logic; port( instrReg : in bit16; port( compout : in std_logic; port( ready : in std_logic; port( progCntrWr : out std_logic; port( progCntrRd : out std_logic; port( addrRegWr : out std_logic; port( outRegWr : out std_logic; port( outRegRd : out std_logic; port( shiftSel : out t_shift; port( aluSel : out t_alu; port( compSel : out t_comp; port( opRegRd : out std_logic; port( opRegWr : out std_logic; port( instrWr : out std_logic; port( regSel : out t_reg; port( regRd : out std_logic; port( regWr : out std_logic; port( rw : out std_logic; port( vma : out std_logic port( ); end component; component alu port( a, b : in bit16; port( sel : in t_alu; port( c : out bit16); end component; component shift port ( a : in bit16; port( sel : in t_shift; port( y : out bit16); end component; component comp port( a, b : in bit16; 305 306 Chapter Thirteen port( sel : in t_comp; port( compout : out std_logic); end component; signal signal signal signal signal signal signal signal begin opdata, aluout, shiftout, instrregOut : bit16; regsel : t_reg; regRd, regWr, opregRd, opregWr, outregRd, outregWr, addrregWr, instrregWr, progcntrRd, progcntrWr, compout : std_logic; alusel : t_alu; shiftsel : t_shift; compsel : t_comp; ra1 : regarray port map(data, regsel, regRd, regWr, data); opreg: trireg port map (data, opregRd, opregWr, opdata); alu1: alu port map (data, opdata, alusel, aluout); shift1: shift port map (aluout, shiftsel, shiftout); outreg: trireg port map (shiftout, outregRd, outregWr, data); addrreg: reg port map (data, addrregWr, addr); progcntr: trireg port map (data, progcntrRd, progcntrWr, data); comp1: comp port map (opdata, data, compsel, compout); instr1: reg port map (data, instrregWr, instrregOut); con1: control port map (clock, reset, instrregOut, com pout, ready, progcntrWr, progcntrRd, addrregWr, out regWr, outregRd, shiftsel, alusel, compsel, opre gRd, opregWr, instrregWr, regsel, regRd, regWr, rw, vma); end rtl; Architecture rtl of entity cpu is a structural implementation of the block diagram Architecture rtl contains the component declarations of all of the components used to build the design, the signals used to connect the components, and the component instantiations to create the functionality After the component and signal declarations are the component instantiation statements that instance the components and connect the appropriate signals In the next few sections, each of the VHDL component descriptions is described in more detail ALU The first entity described is the ALU This entity performs a number of arithmetic or logical operations on one or more input busses A symbol for the ALU is shown in Figure 13-2 CPU: Synthesis Description Figure 13-2 ALU Interface 307 a b sel ALU c Inputs a and b are the two input busses upon which the ALU operations are performed Output bus c returns the result of the ALU operation Input sel determines which operation is performed as specified by Figure 13-3 As we can see, the ALU can perform a number of arithmetic operations, such as add and subtract, and some logical operations, such as AND, OR, and XOR Following is a VHDL description of the ALU entity: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use work.cpu_lib.all; entity alu is port( a, b : in bit16; port( sel : in t_alu; port( c : out bit16); end alu; architecture rtl of alu is begin aluproc: process(a, b, sel) begin case sel is when alupass => c c c c c c c c c c c if a = b then compout