h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 147 Chapter 12 Timers Timers are always used for microcomputer-based control. Since the interrupt function is almost always used as well, review exception handling described in Chapter 7. Although the H8/3048 timers have many channels and various uses are enabled by combining them, this chapter focuses on simple applications only. 12.1 General Timer Overview Most microcomputer-applied systems require time management. Timers are used in the following cases: To execute a program after a certain period of time or at a certain interval. To make an external pin output pulses after a certain period of time or at a certain interval to control operation of externally connected equipment. To measure the high- and low-level periods of pulses input from externally connected equipment to a pin to check and control the equipment status. Although timer functions differ between products and most single-chip microcomputers have several types of timers incorporated in one microcomputer, timers generally have the following structure and functions: Timer basic structure and interrupt request generation by compare match The central component of the timer is a counter called a "timer counter". Although the bit count of the counters differs between products, 8- or 16-bit counters are the mainstream. The counter is designed to count microcomputer internal clocks or clocks input from an external input pin. By counting clocks having known periods, you can determine the elapsed time based on the count. The timer also has a register often called a "compare register", which has the same bit count as the timer counter. In this register, you can write any numeric data using an instruction. The value in the compare register is always compared with the timer count by a comparator, and an event in which both values match is referred to as a "compare match". By using this function, you can generate a compare match when the time obtained by multiplying the clock period counted by the timer counter by the value in the compare register has elapsed. In every timer, a compare match generates an interrupt request. You can manage the time of processing as necessary by h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 148 writing a desired value in the compare register to generate an interrupt after the set time has elapsed. Figure 12.1: Sample Configuration of Timer Having Output Compare and Input Capture Functions Interval timer Specific interrupt handling can be triggered at a certain interval. A timer used in this way is specifically referred to as an "interval timer". Output compare function Some timers are capable of outputting the high- or low-level voltage according to the setting from a dedicated output pin when a compare match occurs. This function is called the "output compare function" or "pulse output function" of the timer. By using a timer with this function, you can output pulses having a desired high- or low-level period. Input capture function Some timers also have a register often called an "input capture register", which has the same bit count as the timer counter. This register is designed to capture the timer counter value when the leading or trailing edge is input to a dedicated input pin. This is called the "input capture function" of the timer. By using a timer with this function, you can measure the high- or low- level period of input pulses. Some timers also have more complicated functions. As described above, timers have various functions and which are provided depends on each h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 149 timer. Except for special dedicated ones, most timers have a function to generate interrupt requests using compare matches. 12.2 ITU Configuration Of the several types of timers incorporated into the H8/3048, this section examines the ITU (Integrated Timer Unit). The ITU has five channels from 0 to 4. Each channel can be used as an independent timer since it is equipped with registers, pulse output/input pins and external clock input pins corresponding to the timer counter, compare register and input capture register. You can also interlock multiple channels. Each channel has almost the same configuration. Figure 12.2 shows the channel 0 block diagram. Figure 12.2: ITU Channel 0 Block Diagram Since each channel has almost the same structure and use, let's take channel 0 as an example. Table 12.1 shows registers relating to channel 0. The "0" suffix represents registers dedicated for channel 0 and other channels also have the same types of registers. The timer counter 0 (TCNT0) is a 16-bit, up counter. There are two general registers 0, A and B (GRA0 and GRB0), which are available as either a compare or input capture register. Since these three 16- bit registers are located at even-numbered addresses in the memory, they are read and written in word-size units. Table 12.1: ITU Channel 0 Register Configuration h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 150 Registers not described here are described in the following sections. Table 12.2 shows the external pins relating to ITU channel 0. There are two TIOC0 pins, A and B, which are used as either pulse output or input pins according to the setting for the uses of the GRA0 and GRB0, either a compare or input capture register. Table 12.2: ITU Channel 0 Pin Configuration 12.3 ITU Registers This section examines ITU channel 0-related registers not described in the previous section. Figure 12.3 shows the timer start register (TSTR), which is not dedicated for channel 0 but commonly used by all channels. This register is designed to start or stop counting by the timer counter of each channel. Figure 12.3: Timer Start Register (TSTR) For channel 0, bit 0 or counter start 0 (STR0) is used and counting is stopped when the STR0 is set at 0 or started when 1. While counting is stopped, no compare match is generated since the TCNT0 is not counted up, no interrupt is generated even if it is enabled, and no pulse is output even if pulse output is enabled. h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 151 12.3.1 Timer Control Register 0 (TCR0) Figure 12.4 shows the timer control register 0 (TCR0), which is designed to set the counting mode for the TCNT0. Figure 12.4: Timer Control Register (TCR0) The timer prescaler bits (TPSC2 to TPSC0) are used to select the clock to be counted. The internal clock can be selected from the system clock φ and the clocks having periods that are twice, four times and eight times as long, and the external clock from four external clock input pins from TCLKA to TCLKD. The clock edge bits (CKEG1 and CKEG0) are used to select the clock edge for counting up when an external clock is selected. If you set to count a clock at both edges, the count is incremented by 2 per clock input. The counter clear bits (CCLR1 and CCLR0) are used to set the timing for clearing the TCNT0 count value. If they are set at 00, the TCNT0 is not cleared but continues counting up permanently. When the count value reaches H'FFFF, however, it automatically returns to H'0000. If they are set at 01 or 10, the TCNT0 is cleared when a compare match or input capture is generated by the GRA0 or GRB0. This setting is convenient for generating compare matches at a certain interval, in other words, for enabling the interval timer, since a value once input to the GRA0 or GRB0 need not be rewritten every time a compare match is generated. Note the following precaution if you set to clear the TCNT0 when a compare match is generated. The TCNT0 count value is not cleared immediately after it reaches the GRA0 or GRB0 value. Instead, it is cleared when the next clock is input or when the counter is counted up next after both values match. Setting of "11" represents synchronous clearing. This lesson, however, omits descriptions of complicated functions such as interlocking of multiple ITU channels. 12.3.2 Timer I/O Control Register 0 (TIOR0) Figure 12.5 shows the timer I/O control register 0 (TIOR0), which is designed to set the uses of the GRA0 and GRB0 as well as those of the corresponding TIOCA0 and TIOCB0 external pins. h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 152 Figure 12.5: Timer I/O Control Register 0 (TIOR0) The I/O control bits A2 to A0 (IOA2 to IOA0) are used to set the uses of the GRA0 and TIOCA0 pins, and the I/O control bits B2 to B0 (IOB2 to IOB0) to set the uses of the GRB0 and TIOCB0 pins. Since they are set in the same way, the following explains how to set the lower 3 bits only. If they are set at 000, the GRA0 is used as an output compare register, which, however, does not output pulses. This setting is used for the interval timer. If they are set at 001, the low-level voltage is output by the TIOCA0 pin when a compare match occurs. If they are set at 010, the high-level voltage is output. If they are set at 011, toggle is output by the TIOCA0 pin when a compare match occurs. Toggle output refers to outputting by inverting the current high/low level. If they are set at 100, the GRA0 is used as an input capture register and input is captured when the leading edge is input to the TIOCA0 pin. If they are set at 101, input is captured when the trailing edge is input to the TIOCA0 pin. Settings 110 and 111 are the same and input is captured at both leading and trailing edges. 12.3.3 Timer Status Register 0 (TSR0) Figure 12.6 shows the timer status register (TSR0), which is designed to collect status flags for notifying compare match or input capture generation. Figure 12.6: Timer Status Register 0 (TSR0) The input capture/compare match flag A (IMFA) is set at 1 when an input capture or compare match occurs in the GRA0. The input capture/compare match flag B (IMFB) is set at 1 when an input capture or compare match occurs in the GRB0. The overflow flag (OVF) is set at 1 when the TCNT0 value is changed from H'FFFF to H'0000. 12.3.4 Timer Interrupt Enable Register 0 (TIER0) Figure 12.7 shows the timer interrupt enable register 0 (TIER0), which disables or enables interrupt requests corresponding to each status flag of the TSR0. h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 153 Figure 12.7: Timer Interrupt Enable Register 0 (TIER0) This register is designed to enable or disable requests for three types of interrupts which can be generated from ITU channel 0, namely, IMIA0, IMIB0 and OVI0 interrupts. For example, if you want to trigger an IMIA0 interrupt request when the IMFA flag of the TSR0 is set at 1, set bit 0 of this register (input capture/compare match interrupt enable A, or IMIEA) at 1. Likewise, the input capture/compare match interrupt enable B (IMIEB) and overflow interrupt enable (OVIE) correspond to the IMFB and OVF of the TSR0 and are designed to enable or disable IMIB0 or OVI0 interrupts, respectively. 12.4 Sample Use as Interval Timer Let's consider an example to turn an LED on at a 25ms interval using ITU channel 0. Here, we write 0 to unused bits of each register. The H8/3048 is assumed to operate at 20MHz. - TCR0 setting For ITU operation, the internal clock φ (phi)/8 is used to set the GRA0 to 25ms and the TCNT0 is used for counting. A compare match occurs every 25ms to clear the TCNT0 and start next counting operation. To enable this, the TCR0 is set as follows. Setting the φ/8 clock enables 25ms setting using 16 bits of the GRA. - GRA0 setting If the φ/8 clock source is selected when the CPU clock is set at 20MHz, one count is equal to 0.5 microsecond. Since 25ms (25000 microseconds) are equal to 62500 counts, set GRA0 to 62499 (62500 - 1). The reason why one is subtracted is that it takes one-clock time after a compare match occurs until the TCNT0 is cleared. - TIOR0 setting Since output pins are not used, the TIOR0 is set as follows: h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 154 - TIER0 setting As for interrupts, only the IMIA0 is used. - TSTR setting Start channel 0 after all settings are completed. C Language Sample #include <machine.h> #include "iodefine.h" /* include I/O address define header file */ /* stack area size */ #pragma stacksize 0x100 void initITU(void) ; /* Power ON Reset function */ __entry(vect=0) void main(void) { initITU() ; PA.DDR = 0x01 ; /* PA0 output */ set_ccr(0) ; /* enable interrupt */ while(1) ; /* endless loop */ } void initITU(void) { ITU0.TCR.BYTE = 0x23 ; /* counter clear GRA,1/8 clock */ ITU0.TIER.BIT.IMIEA = 1 ; /* enable IMIA interrupt */ ITU0.GRA = 62500-1 ; /* 20MHz/40Hz(25ms)/8 = 62500 */ ITU.TSTR.BIT.STR0 = 1 ; /* start ITU0 */ } // vector 24 IMIA0 __interrupt(vect=24) void INT_IMIA0(void) { ITU0.TSR.BIT.IMFA = 0 ; /* clear IMFA , stop interrupt request */ PA.DR.BIT.B0 = ~PA.DR.BIT.B0 ; /* inverse PA0 terminal */ } h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 155 This concludes the description of a sample program using timers. h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 156 1. What are the following functions provided for the ITU called? Enter an appropriate word in parentheses. Answer To trigger specific interrupt handling at a certain interval. ¼(Interval timer) function To output the high/low-level voltage from an external pin after a certain period of time.¼(Output compare) function To capture the timer counter value when the leading/trailing edge is input in an external pin to another register. ¼(Input capture) function Refer to 12.1 to understand the general timer overview. 2. The following describes the compare match function of the ITU. Enter an appropriate word in parentheses. Answer In ITU channel 0, a compare match is generated by the GRA0 when the time obtained by multiplying the (period) of pulses counted by the (TCNT0) by the value in the GRA0 has elapsed. Refer to 12.1 and 12.2 to understand how a compare match is generated. 3. The following describes the functions available when a compare match is generated by the GRB0 of ITU channel 0. Enter an appropriate word in parentheses. Answer The (IMIB0) interrupt can be generated. The (high/low-level voltage) can be output from the (TIOCB0) external pin. Listen to the explanation provided in "Figure 12.2: ITU Channel 0 Block Diagram" in 12.2 to understand how channel 0 generates two compare matches, A and B. 4. You want to generate an interrupt using the GRA0 of ITU channel 0 but without outputting pulses when a compare match occurs. How do you set the TIOR0 and TIER0? Answer Write (000) to the 3 bits from (I/O control bits A2 to A0 (bit 2 to bit 0)) of the TIOR0. Write (1) to the (IMIEA) bit of the TIER0. Refer to 12.3.2 and 12.3.4 to understand how the TIOR0 and TIER0 are used. 5. What happens if a compare match occurs using the GRB0 of ITU channel 0? . t t p : / / r e s o u r c e . r e n e s a s . c o m Page 147 Chapter 12 Timers Timers are always used for microcomputer-based control. Since the interrupt. most single-chip microcomputers have several types of timers incorporated in one microcomputer, timers generally have the following structure and functions: