Chapter 11 Serial Interface (SCI) The serial interface is a communication function having two types: start-stop synchronization and clock synchronization This chapter describes the start-stop synchronization type, which has a wider range of applications Although a multiprocessor function is added to the H8/3048 serial interface, this function is not explained here since it is specific to the series and not provided for other processors The serial interface has more registers than peripheral functions described earlier and the operation may seem more complex You need to completely understand the meaning of the settings regarding the contents of each register Since the training board is connected to your PC through the serial interface, you can use the PC as I/O equipment by developing a program to send and receive characters using ASCII codes Note The following register has negative logic bit names: 11.1 Serial Data Input/Output and Its Method In a microcomputer-applied system, several bits of digital data are sometimes input or output through time-division using one pin These timedivided bits of digital data are called "serial data" and the function for inputting/outputting serial data is called the "serial port" Although the serial port has a different name on some products, it is referred to as the "serial communication interface" (hereinafter referred to as the "SCI") in the H8/3048 Although data input/output using the serial port takes longer time than that using the I/O port you learned about in Chapter 8, it uses fewer signal lines for exchanging data with other parties (such as microcomputers, equipment and devices) http://resource.renesas.com Page 129 Figure 11.1: Serial Data Input/Output As such, the serial port is mostly used for input/output with more distant parties, for which connection using a large number of signal lines is unsuitable Data input/output using the serial port is often referred to as "communication", with input being referred to as "reception" and output "transmission" Serial data communication is conducted via the RS-232C and USB (Universal Serial Bus) ports, used to connect PCs and peripherals, as well as data communication using Ethernet or telephone lines Figure 11.2: Serial Data Formats http://resource.renesas.com Page 130 Start-stop synchronization communicates 7- or 8-bit data per operation and the transmit pin outputs the high-level voltage while data are not transmitted When transmission is started, the start bit, one bit of the low-level voltage, is output to notify the other party of the start of data transmission and 7- or 8-bit data are output After that, the parity bit is output if an error is detected At the end of transmission, the stop bit, a high-level voltage, is output, which consumes one or two bits As shown above, start-stop synchronization has several data formats There are two requirements to communicate through start-stop synchronization: one is for the sender and receiver to use the same data format and the other is for them to use the same transmission speed (also called "baud rate", which refers to how many bits are communicated per second; the unit is bit per second, or bps) Communication will fail unless these two are predetermined between sender and receiver 11.2 SCI Operation Overview The H8/3048 has two SCI channels which can be set to either start-stop synchronization or clock synchronization Although the figure below shows a block diagram of only one SCI channel, both have the same configuration and use Figure 11.3: SCI Block Diagram For transmission, the CPU writes the data to be transmitted in the transmit data register (TDR) After that, the SCI moves the data from the TDR to the transmit shift register (TSR), which outputs them from the transmit pin http://resource.renesas.com Page 131 (TxD) bit by bit in the set data format through some modification such as adding the start or stop bit For reception, the data input in the receive pin (RxD) are stored in the receive shift register (RSR) bit by bit through some modification such as removing the start or stop bit After that, the SCI moves the data from the RSR to the received data register (RDR) when the stop bit arrives and the CPU reads them using the MOV instruction In communication using the SCI, the data to be transmitted are written in the TDR and the received data are read from the RDR Although the TSR and RSR exist inside the SCI, they are not assigned an address in the memory since users need not operate them The SCI has four more registers for controlling other settings such as communication operation, which are described in the following section 11.3 SCI Registers Table 11.1 shows the SCI register configuration The following explains how to transmit and receive serial data using the SCI in sequence together with introduction of each register Table 11.1: SCI Register Configuration (for Channels) 11.3.1 Communication Mode and Data Format Setting The SCI is equipped with a serial mode register (SMR), which is designed to set the communication mode and data format Figure 11.4: Serial Mode Register (SMR) http://resource.renesas.com Page 132 C/A CHR PE O/E STOP MP CKS The communication mode bit is designed to set use of start-stop or clock synchronization Bits to are effective only when this bit is set to The character length bit is designed to set the data bit length The parity enable bit is designed to set use of parity bit or not The parity mode bit is designed to set even or odd parity when the parity bit is set to be used If it is set not to be used, the setting of this bit is ineffective The stop bit length bit is designed to set the stop bit length The description of the multiprocessor mode bit is omitted in this lesson The lower clock select bits are designed to select the clock to be used to generate the baud rate among four using a combination of and The SCI communication speed is determined by three factors, one of which is the clock select bits How it is determined is described in detail in the next section 11.3.2 Setting of Communication Speed Figure 11.5 shows the bit rate register (BRR), which is used to determine the communication speed Figure 11.5: Bit Rate Register (BRR) The SCI communication speed is determined by the following three factors: Clock select bits in the SMR (CKS1 and CKS0) Value written in the BRR Microcomputer operating frequency (same as the oscillating frequency of the crystal oscillator externally connected to the microcomputer) Table 11.2 shows how the communication speed is determined by these three factors For example, to set the communication speed to 9600 bauds (the same unit as bps) when the microcomputer operating frequency is 20MHz (same as when the crystal XTAL is 20MHz), read the values of N and n from this table N refers to the value to be set in the BRR and n to the one to be set in the clock select bits in the SMR Since N = 64 and n = at 9600 bauds, the clock select bits (CKS1 and CKS0) are both A communication speed of 9600 bauds can be achieved by writing these values in each register Table 11.2: Sample Settings of BRR for Baud Rates (Start-stop Synchronization) http://resource.renesas.com Page 133 11.3.3 Communication Procedure Figure 11.6 shows the serial status register (SSR), which is an important register for transmitting or receiving data Figure 11.6: Serial Status Register (SSR) All of the upper bits of this register serve as the status flag If you are not sure about the use, review how to use each flag The lower bits are not described here since they are not used so often TDRE The transmit data register empty (TDRE) flag is used for transmitting data Refer to Figure 11.7 for the transmission procedure Before writing the data to be transmitted in the transmit data register (TDR), make sure that the TDRE is set to If it is still set to 0, you should not write data in the TDR yet If the TDRE is set to 1, write the data to be transmitted in the TDR, then be sure to clear the TDRE to using the BCLR instruction or by other means When the TDRE is cleared to 0, the SCI starts transmission It automatically sets the TDRE to after completely moving the data from the TDR to the TSR This is why you should write data in the TDR after the TDRE has been set to http://resource.renesas.com Page 134 RDRF The received data register full (RDRF) flag is used for receiving data For the reception procedure, also refer to Figure 11.7 The SCI automatically sets the RDRF to after completely moving the received data from the RSR to the received data register (RDR) So, make sure that the RDRF is set to before reading the received data from the RDR If it is still set to 0, you should not read the data yet If the RDRF is set to 1, read the received data from the RDR, then be sure to clear the RDRF to using the BCLR instruction or by other means After the RDRF is cleared to 0, the SCI is allowed to move the data received next from the RSR to the RDR If the next data is received before the RDRF is cleared to 0, the SCI cannot move the received data from the RSR to the RDR, resulting in an overrun error (described later) Accordingly, be sure to clear the RDRF to after reading the received data from the RDR Figure 11.7 shows the transmission and reception procedures described above in the form of flowcharts Figure 11.7: Data Transmission/Reception Flowcharts Receive error The SSR has three error flags Although no transmission errors occur since data are unilaterally sent, errors sometimes occur during reception since the receiver may fail to receive what the sender has transmitted The three types of errors all occur during reception http://resource.renesas.com Page 135 Figure 11.8: Receive Error 11.3.4 Enabling/Disabling Communication or Interrupts Figure 11.9 shows the serial control register (SCR), which is designed to enable or disable transmission/reception or interrupts The lower bits are not described here TIE RIE Figure 11.9: Serial Control Register (SCR) The transmit interrupt enable bit is designed to enable or disable the transmitted data empty interrupt (TXI) When this bit is set to 1, the TXI interrupt is generated when the TDRE in the SSR is set to (when the system is ready to write the data to be transmitted to the TDR) The receive interrupt enable bit is designed to enable or disable the received data full interrupt (RXI) and receive error interrupt (ERI) Although there are two types of reception-related interrupts, RXI and ERI, you cannot enable or disable them separately This bit is used to collectively enable or disable both interrupts When this bit is set to 1, the RXI interrupt is generated when the RDRF in the SSR is set to (when the system is ready to read the received data from the RDR) The ERI interrupt is generated whenever any of the three flags in the SSR, namely, overrun error (ORER), framing error (FER) and parity error (PER), is set to (whenever a certain receive error occurs) http://resource.renesas.com Page 136 TE and RE The transmit enable (TE) and receive enable bits are designed to enable or disable SCI transmission and reception, respectively Unless these bits are set to 1, no transmission or reception is conducted To initialize or change SCI settings such as communication mode, data format and communication speed, on the other hand, they must be set to Now that descriptions of the SCI registers are completed, let's proceed to some sample uses of the SCI 11.4 Sample SCI Uses This section introduces programs to transmit and receive one-character data (8-bit data) written in ASCII code through start-stop synchronization using the SCI0 The following specifications are assumed here, and hardware design and register value settings are conducted accordingly • • • • • • Data transfer mode and level Data transfer speed Data transfer format Multiprocessor function SCI clock Interrupts during data transfer Start-stop synchronization (RS-232C level) 9600 bauds 8-bit data, stop bit, and no parity bit Not used Internal (the H8/3048 operates at 20MHz) Interrupts are used for reception As for the hardware, the H8/3048 signal level (5V, 0V) must be changed to the RS-232C level (±12V) For this purpose, an RS-232C line driver/receiver IC as shown in Figure 11.10 is used Although an RS-232C device also has modem control signals in addition to TxD and RxD pins, it is assumed that these signals be not used since they are not supported by the H8/3048 Figure 11.10: Hardware for Start-stop Synchronization Data Transfer Using SCI0 http://resource.renesas.com Page 137 11.4.1 SCI Initialization Program Since programs using the SCI tend to be complicated, let's start by taking a look at a program to conduct SCI initialization only Each register of the SCI0 to be used is set as follows by default: Figure 11.11: SCI0 Register Default Settings Now that the register default values are determined, the following explains a sample program to initialize the registers This program is designed as a subroutine to be called from the main routine Since reception will fail if the reception-related status flags have been set before each register is initialized or reception is started, clear the flags after dummy-reading the SSR They are not cleared unless zero is written after reading Dummy read refers to reading conducted only for satisfying this condition even though flag values need not be checked If B'00000000 is written at this time, the TDRE is also cleared, mistakenly transmitting data stored in the TDR, if any To prevent this, write http://resource.renesas.com Page 138 B'10000000 so that the TDRE is not cleared (nothing happens by writing in the TDRE) The SSR need not be initialized if nothing is done after resetting C Language Sample #include "iodefine.h" void initSCI(void) ; void initSCI(void) { int i ; SCI0.SCR.BYTE = ; /* stip SCI0 , use internal clock */ SCI0.SMR.BYTE = ; /* asynchronouse mode,8 bit data,1stop,no-parity,1/1 clock*/ SCI0.BRR = 64 ; /* 20MHz / 9600 / 32 -1 = 64 */ for(i=0;i