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A computer system consists of a processor, memory, I/O, and the interconnections among these major components. With the exception of the processor, which is suffi- ciently complex to devote Part Three to its study, Part Two examines each of these components in detail.
PART TWO The Computer System P.1 ISSUES FOR PART TWO A computer system consists of a processor, memory, I/O, and the interconnections among these major components. With the exception of the processor, which is suffi ciently complex to devote Part Three to its study, Part Two examines each of these components in detail ROAD MAP FOR PART TWO Chapter 3 A TopLevel View of Computer Function and Interconnection At a top level, a computer consists of a processor, memory, and I/O compo nents. The functional behavior of the system consists of the exchange of data and control signals among these components. To support this exchange, these components must be interconnected. Chapter 3 begins with a brief examina tion of the computer’s components and their input–output requirements. The chapter then looks at key issues that affect interconnection design, especially the need to support interrupts. The bulk of the chapter is devoted to a study of the most common approach to interconnection: the use of a structure of buses Chapter 4 Cache Memory Computer memory exhibits a wide range of type, technology, organiza tion, performance, and cost. The typical computer system is equipped with a hierarchy of memory subsystems, some internal (directly accessible by the processor) and some external (accessible by the processor via an I/O module) Chapter begins with an overview of this hierarchy. Next, the chapter deals in detail with the design of cache memory, including sepa rate code and data caches and twolevel caches 63 Chapter 5 Internal Memory The design of a main memory system is a neverending battle among three competing design requirements: large storage capacity, rapid access time, and low cost As memory technology evolves, each of these three characteristics is changing, so that the design decisions in organizing main memory must be revisited anew with each new implementation. Chapter 5 focuses on design issues related to internal memory First, the nature and organization of semiconductor main memory is examined Then, recent advanced DRAM memory organizations are explored Chapter 6 External Memory For truly large storage capacity and for more permanent storage than is available with main memory, an external memory organization is needed The most widely used type of external memory is magnetic disk, and much of Chapter 6 concentrates on this topic. First, we look at magnetic disk technology and design considerations. Then, we look at the use of RAID organization to improve disk memory performance. Chapter 6 also examines optical and tape storage Chapter 7 Input/Output I/O modules are interconnected with the processor and main memory, and each controls one or more external devices. Chapter 7 is devoted to the var ious aspects of I/O organization. This is a complex area, and less well under stood than other areas of computer system design in terms of meeting performance demands. Chapter 7 examines the mechanisms by which an I/O module interacts with the rest of the computer system, using the tech niques of programmed I/O, interrupt I/O, and direct memory access (DMA) The interface between an I/O module and external devices is also described Chapter 8 Operating System Support A detailed examination of operating systems (OSs) is beyond the scope of this book. However, it is important to understand the basic functions of an operating system and how the OS exploits hardware to provide the de sired performance. Chapter 8 describes the basic principles of operating systems and discusses the specific design features in the computer hard ware intended to provide support for the operating system. The chapter begins with a brief history, which serves to identify the major types of op erating systems and to motivate their use. Next, multiprogramming is ex plained by examining the longterm and shortterm scheduling functions Finally, an examination of memory management includes a discussion of segmentation, paging, and virtual memory 64 CHAPTER A TOPLEVEL VIEW OF COMPUTER FUNCTION AND INTERCONNECTION 3.1 Computer Components 3.2 Computer Function Instruction Fetch and Execute Interrupts I/O Function 3.3 Interconnection Structures 3.4 Bus Interconnection Bus Structure MultipleBus Hierarchies Elements of Bus Design 3.5 PCI Bus Structure PCI Commands Data Transfers Arbitration 3.6 Recommended Reading and Web Sites 3.7 Key Terms, Review Questions, and Problems Appendix 3A Timing Diagrams 65 At a top level, a computer consists of CPU (central processing unit), memory, and I/O components, with one or more modules of each type. These components are intercon nected in some fashion to achieve the basic function of the computer, which is to exe cute programs.Thus, at a top level, we can describe a computer system by (1) describing the external behavior of each component—that is, the data and control signals that it exchanges with other components; and (2) describing the interconnection structure and the controls required to manage the use of the interconnection structure This toplevel view of structure and function is important because of its explana tory power in understanding the nature of a computer. Equally important is its use to understand the increasingly complex issues of performance evaluation. A grasp of the toplevel structure and function offers insight into system bottlenecks, alternate path ways, the magnitude of system failures if a component fails, and the ease of adding per formance enhancements In many cases, requirements for greater system power and failsafe capabilities are being met by changing the design rather than merely increas ing the speed and reliability of individual components This chapter focuses on the basic structures used for computer component in terconnection. As background, the chapter begins with a brief examination of the basic components and their interface requirements Then a functional overview is provided. We are then prepared to examine the use of buses to interconnect system components 3.1 COMPUTER COMPONENTS As discussed in Chapter 2, virtually all contemporary computer designs are based on concepts developed by John von Neumann at the Institute for Advanced Studies, Princeton. Such a design is referred to as the von Neumann architecture and is based on three key concepts: 3.1 / COMPUTER COMPONENTS 67 • Data and instructions are stored in a single read–write memory • The contents of this memory are addressable by location, without regard to the type of data contained there • Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next The reasoning behind these concepts was discussed in Chapter 2 but is worth summarizing here. There is a small set of basic logic components that can be com bined in various ways to store binary data and to perform arithmetic and logical op erations on that data If there is a particular computation to be performed, a configuration of logic components designed specifically for that computation could be constructed. We can think of the process of connecting the various components in the desired configuration as a form of programming. The resulting “program” is in the form of hardware and is termed a hardwired program Now consider this alternative. Suppose we construct a generalpurpose config uration of arithmetic and logic functions. This set of hardware will perform various functions on data depending on control signals applied to the hardware. In the orig inal case of customized hardware, the system accepts data and produces results (Figure 3.1a). With generalpurpose hardware, the system accepts data and control signals and produces results Thus, instead of rewiring the hardware for each new program, the programmer merely needs to supply a new set of control signals How shall control signals be supplied? The answer is simple but subtle. The en tire program is actually a sequence of steps. At each step, some arithmetic or logical Data Results (7.a) Programming in hardware Instruction codes Control signals Data Results (7.b) Programming in software Figure 3.1 Hardware and Software Approaches operation is performed on some data. For each step, a new set of control signals is needed. Let us provide a unique code for each possible set of control signals, and let us add to the generalpurpose hardware a segment that can accept a code and gen erate control signals (Figure 3.1b) Programming is now much easier. Instead of rewiring the hardware for each new program, all we need to do is provide a new sequence of codes. Each code is, in effect, an instruction, and part of the hardware interprets each instruction and gen erates control signals. To distinguish this new method of programming, a sequence of codes or instructions is called software Figure 3.1b indicates two major components of the system: an instruction in terpreter and a module of generalpurpose arithmetic and logic functions. These two constitute the CPU Several other components are needed to yield a functioning computer. Data and instructions must be put into the system. For this we need some sort of input module. This module contains basic components for accepting data and instructions in some form and converting them into an internal form of signals us able by the system. A means of reporting results is needed, and this is in the form of an output module. Taken together, these are referred to as I/O components One more component is needed. An input device will bring instructions and data in sequentially. But a program is not invariably executed sequentially; it may jump around (e.g., the IAS jump instruction). Similarly, operations on data may re quire access to more than just one element at a time in a predetermined sequence. Thus, there must be a place to store temporarily both instructions and data That module is called memory, or main memory to distinguish it from external storage or peripheral devices. Von Neumann pointed out that the same memory could be used to store both instructions and data Figure 3.2 illustrates these toplevel components and suggests the interactions among them The CPU exchanges data with memory For this purpose, it typically makes use of two internal (to the CPU) registers: a memory address register (MAR), which specifies the address in memory for the next read or write, and a memory buffer register (MBR), which contains the data to be written into memory or receives the data read from memory Similarly, an I/O address register (I/OAR) specifies a particular I/O device. An I/O buffer (I/OBR) register is used for the ex change of data between an I/O module and the CPU A memory module consists of a set of locations, defined by sequentially num bered addresses. Each location contains a binary number that can be interpreted as either an instruction or data. An I/O module transfers data from external devices to CPU and memory, and vice versa. It contains internal buffers for temporarily hold ing these data until they can be sent on Having looked briefly at these major components, we now turn to an overview of how these components function together to execute programs 3.2 COMPUTER FUNCTION The basic function performed by a computer is execution of a program, which con sists of a set of instructions stored in memory. The processor does the actual work by executing instructions specified in the program. This section provides an overview of ... well under stood than other areas of computer system design in terms of meeting performance demands. Chapter 7 examines the mechanisms by which an I/O module interacts with the rest of the computer system, ... With synchronous access, the DRAM moves data in and out under control of the system clock The processor or other master issues the instruction and address information, which is latched by the DRAM. The DRAM then responds ... How many wait states do we have to insert per memory read operation if the ac cess time of the DRAMs is 150 ns? The memory of a particular microcomputer is built from 64K * 1 DRAMs. Accord ing to the data sheet, the cell array of the DRAM is organized into 256 rows. Each