Lời giải chương 6 Digital Arithmetic: Operations and Circuits bộ môn hệ thống số

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Lời giải chương 6 Digital Arithmetic: Operations and Circuits bộ môn hệ thống số. Lời giải bao gồm các bài tập trong sách Digital Systems Principles and Applications 11th edition giúp sinh viên rèn luyện thêm khả năng tư duy giải bài tập. Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition CHAPTER SIX - Digital Arithmetic: Operations and Circuits 6.1 (a) 1010 1011 + 10101 (b) 1111 0011 + 10010 (c) 1011.1101 0011.1000 + _ 1111.0101 (d) 0.1011 0.1111 + 1.1010 (e) 10011011 10011101 + 100111000 (f) 1010.01 0010.111 + 1101.001 (g) 10001111 01010001 + 11100000 (h) 11001100 00110111 + _ 100000011 (i) 110010100011 011101111001 + _ 1010000011100 (j) 1010 0111 - 0011 (k) 101010 100101 - _ 000101 (l) 1111.010 1000.001 - _ 0111.001 (m) (n) 11100010 01010001 - 10010001 (o) 100010.1001 001111.0010 - _ 010011.0111 10011 00110 - 01101 (p) 1011000110 1001110100 - 0001010010 6.2 6.3 (a) +3210=001000002 (c) +6310=001111112 (e) +12710 = 011111112 (g) +8910 = 010110012 (i) -110 = 111111112 (k) Can't be represented with eight bits (l) 010=000000002 (n) +310=000000112 (p) Can't be represented with eight bits (b) -1410=111100102 (d) -10410=100110002 (f) -12710 = 100000012 (h) -5510 = 110010012 (j) -12810 = 100000002 (a) (c) (e) (g) (i) (b) (d) (f) (h) (j) 011012=1310 011110112=+12310 011111112=+12710 111111112=-110 011000112=9910 (m) +8410 = 0010101002 (o) -310 = 111111012 111012=-310 100110012=-10310 100000002=-12810 100000012=-12710 110110012=-3910 _ 85 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 6.4 (a) Eleven magnitude bits can represent decimal numbers from -211 to +(211-1) or -204810 to 204710 (b) -32,768=-2N -> N=15 (for magnitude) Thus, sixteen bits are required including sign bit 6.5 Four magnitude bits can represent numbers from -1610 to +1510 6.6 Dec number _8-bit signed number 2's-comp (Negate) (a) +7310 -> 01001001 -> 101101112 = (-7310) (b) -1210 -> 11110100 -> 000011002 = (+1210) (c) +1510 -> 00001111 -> 111100012 = (-1510) (d) -110 > 11111111 -> 000000012 = (+110) (e) -12810 -> 100000002 ->It requires nine binary bits to represent +12810= 0100000002 (f) +12710 ->011111112 ->100000012 = (-12710) 6.7 (a) With 10 bits, we can represent any unsigned number from to 102310 With 10 bits, we can represent signed numbers from -29 to +(29-1), or -51210 to +51110 (b) With bits, we can represent any unsigned number from to 25510 With bits, we can represent signed numbers from -27 to +(27-1), or -12810 to +12710.Using 8-bits 6.8 (a) +1210= 00001100 (b) -1210= 10001100 (c) (00001100 + 10001100) = 10011000  ?? 6.9 (a) +9 = +6 = 00001001 00000110 + 00001111 = +15 (b) +14 = -17 = 00001110 11101111 + 11111101 = -3 (c) +19 = -24 = 00010011 11101000 + 11111011 = -5 (d) -48 = -80 = 11010000 10110000 + 10000000 = -128 (e) +17 = -16 = 00010001 11110000 + 00000001 = +1 (f) -13 = -21 = 11110011 11101011 + 11011110 = -34 (g) +47 = -47 = 00101111 11010001 + 00000000 = (h) -15 = +36 = 11110001 00100100 + 00010101 = +21 (i) +17 = -17 = 00010001 11101111 + 00000000 = (j) Same as (i) _ 86 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 6.10 (k) +68 = +45 = 01000100 00101101 + 01110001 = 113 (l) +77 = +50 = 01001111 00110010 + _ 01111111= +127 (a) +37 = +95 = (b) -95 +(-37) = 10100001 = 11011011 + _ 01111100 (Sign bit=0 indicates overflow.) (c) -37 +(-95) = 11011011 = 10100001 + _ 01111100 (Sign bit=0 indicates overflow.) (d) 95 -(-37) = 01011111 = 00100101 + _ 10000100 (Sign bit=1 indicates overflow.) 00100101 01011111 + _ 10000100 (Sign bit=1 indicates overflow.) 6.11 _ 87 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 6.12 12/4=3 63/9=7 23/4=5.75 22.8125/1.5=15.1875 (e) 1100011/1001 = 1011 6.13 a) d) 0111 0100 0010 0011 + 1001 0111(BCD) (f) 100111011/1111 = 10101 b) 0101 1000 c) 0001 0100 0111 0011 0111 0011 1000 0000 + + _ 1000 1111 0100 1100 0111 + 0110 + 0110 _ _ 1001 0101(BCD) 0101 0010 0111(BCD) 0011 1000 0101 0001 0001 1000 + 0100 1001 1101 + 0110 0100 1010 0011 + 0110 0101 0000 0011(BCD) e) 1001 1001 1000 0000 0000 0011 + _ 1001 1001 1011 + 0110 1001 1010 0001 + 0110 1010 0000 0001 + 0110 0001 0000 0000 0001(BCD) _ 88 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition f) 0110 0010 0011 0101 1001 1001 + 1011 1011 1100 0110 0110 0110 0001 0010 0010 0010(BCD) g) 0101 0101 0101 0010 0111 0100 + 0111 1100 1001 0000 0110 0000 1000 0010 1001(BCD) h) 0100 1000 0111 0001 0001 0110 + 0101 1001 1101 0000 0000 0110 0101 1010 0011 0000 0110 0000 0110 0000 0011(BCD) 6.14 (a) 3E91 + 2F93 = 6E24 (b) 91B + 6F2 = 100D (c) ABC + DEF = 18AB (d) 2FFE + 0002 = 3000 (e) FFF + 0FF = 10FE (f) D191 + AAAB = 17C3C (g) 5C74 + 22BA = 7F2E (h) 39F0 + 411F = 7B0F 6.15 (a) 3E91 - 3E91 2F93 D06D (2's complement) - _ + _ (Ignore carry) -> 10EFE 0300 - 0300 005A - FFA6 - + (Ignore carry) -> 102A6 (b) 91B 91B 6F2 - 90E - _ + (Ignore carry) -> 1229 (c) (d) (e) (f) F000 - F000 EFFF - 1001 - + _ (Ignore carry) -> 10001 0200 -0200 0003 -FFFD - + _ (Ignore carry) -> 101FD 2F00 2F00 4000 C000 - + EF00 _ 89 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition (g) 6.16 9AE5 9AE5 C01D - 3FE3 - + _ DAC8 03FF 0200 - _ 01FF +1 _ 0200 7FD0 4000 - _ 3FD0 +1 _ 3FD1 (h) 4321 4321 F165 0E9B - + 51BC } 0200 } 3FD1 } + } 41D116 locations=1684910 } } } 6.17 (a) 7716 = 11910 (b) 7716 = +11910 (c) E516 = 22910 ; E516 = -2710 6.18 One possibility is to convert each EX-OR to its NAND equivalents shown below: Then, convert ANDs and OR gate for COUT to their equivalent NAND representation 6.19 6.21 6.22 After the PGT of the LOAD pulse, the FFs in the B register require 30ns to produce proper levels to the FAs The FAs produce stable outputs in 4x40ns or 160ns (allowing for carry propagation) These outputs have to be present at the inputs of the A register for 10ns (set-up time) before the PGT of the TRANSFER pulse The total time, then, is 200ns _ 90 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 6.23 6.24 Overflow Circuit One possibility: _ 91 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 6.25 Final expression for C3 can be put into S-of-P form by multiplying all terms out This results in a circuit with TWO levels of gating The arrangement of Figure 6.9 requires that A0, B0, and C0 propagate through as many as levels of gates before producing C3 6.26 A[7 0] = 11101100; B[7 0] = 01000011; C8 = 1; [7 0] = 00101111 6.27 (a) SUM = 0111 (b) SUM = 1010 (-6) (c) SUM = 1100 (-4) 6.28 (a) C4 C0 1 1 1 A 1 0 B _ 1 Σ (-6) (b) C4 C0 1 0 A 0 B _ 1 Σ (-2) (b) (c) C4 C0 1 1 1 A 1 B _ 1 Σ (+7) 6.29 (a) 1 1 A 0 B _ 1 Σ (+7) No Overflow 1 0 A 1 B _ 1 Σ (-6) No Overflow (c) 1 0 A 0 0 B _ 1 0 Σ (-4) No Overflow _ 92 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 6.30 (a) 6.31 No Overflow (b) No Overflow (c) Overflow Three 74HC00 chips will have a total of twelve 2-input NAND gates I Replace all of the 2-input AND gates (gates 1, 2, 3, 4, 5, 6, 7, and 8) with 2-input NAND gates II Replace all of the 2-input OR gates (gates 9, 10, 11, and 12) with 2-input NAND gates 6.32 An EX-OR used as a controlled inverter with X as the control input can be connected as shown below for each B FF 6.33 (a) [S]=011 will select the A plus B operation: [A]=0110; [B]=0011; therefore, F=1001, C N+4=0, OVR=1 (b) [S]=001 will select the B minus A operation: [A]=0110; [B]=0011; therefore, F=1101, CN+4=0, OVR=0 (c) [S]=010 will select the A minus B operation: [A]=0110; [B]=0011; therefore, F=0011, CN+4=1, OVR=0 6.34 [S] = 100 will select the Exclusive-OR operation: [A] = XXXX; [B] = 1111 Therefore, F = [ A] 6.35 (a) [S] = 110 will select the AND operation: [A] = 10101100; [B] = 00001111; therefore, =00001100 (b) [S] = 100 will select the Exclusive-OR operation:[A] = 11101110; [B] = 00110010; therefore, =11011100 6.36 [S] = 100 to select the Exclusive-OR operation Thus, the  outputs will be zero when [A] = [B] The NORed result of the output sums 0-7 will indicate whether or not the binary numbers are equal (X=1) The output X of the NOR gate is HIGH when [A]=[B] _ 93 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 6.37 (a) After 0010 is transferred into the A register, [A] = 0010 After [A] is added to 0011 the result should be 0101 However, because bit A2 is stuck LOW the final results in [A] = 0001 (b) [A] = 1010 (c) After 0111 is transferred into the A register, [A] = 0011 After [A] is added to 0011 the result should be 0110 However, because bit A2 is stuck LOW the final results in [A] = 0010 (d) [A] = 1011 (e) After 1001 is transferred into the A register, [A] = 1001 After [A] is added to 0011 the result should be 1100 However, because bit A2 is stuck LOW the final results in [A] = 1000 6.38 The technician most likely connected input C0 of the 4-bit parallel adder to the ADD signal instead of the SUB signal 6.39 (a) B[3 0] would all be HIGH (b) C0 would be HIGH (c) Σ [3 0] would always contain the value from the accumulator, which would never change because it is adding to the accumulator 11112 plus a carry in of resulting in the same value that was in the accumulator (d) C4 will always be HIGH 6.40 (a) or (b) example answers 6.41 _ 94 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 6.42 AHDL VHDL PORT( a [7 0], b[7 0] z[7 0] :INPUT; :OUTPUT; a, b z :IN :OUT BIT_VECTOR (7 DOWNTO 0; BIT_VECTOR (7 DOWNTO 0); 6.43 (a) 000100 (b)10111111 (c) 1000100 (d) 1000000 (e) 0101110 6.44 (a) a[3 0] = 0111 6.45 (a) 6.46 AHDL (b) (b) b[0] = (c) a[7] = (c) 0010110 z[6 0] = a[7 1] z[7] = a[0]; VHDL z(6 0) c[0] = cin; f[] = a[] $ !b[] $ c[3 0]; generate sum c[4 1] = (a[] & !b[]) # (a[] & c[3 0]) # (!b[] & c[3 0]); cout = c[4]; carry out ovr = c[4] $ c[3]; generate signed overflow indicator WHEN B"011" => c[0] = cin; f[] = a[] $ b[] $ c[3 0]; generate sum c[4 1] = (a[] & b[]) # (a[] & c[3 0]) # (b[] & c[3 0]); cout = c[4]; carry out ovr = c[4] $ c[3]; generate signed overflow indicator WHEN B"100" => f[] = a[] $ b[]; cout = GND; ovr = GND; WHEN B"101" => f[] = a[] # b[]; cout = GND; ovr = GND; WHEN B"110" => f[] = a[] & b[]; cout = GND; ovr = GND; WHEN B"111" => f[] = B"1111"; cout = GND; ovr = GND; END CASE; END; 6.52 (a) Full Adder - Logic circuit with three inputs and two outputs The inputs are a carry bit (C IN) from a previous stage, a bit from the Augend, and a bit from the addend, respectively The outputs are the sum bit produced by the addition of the bit from the addend with the bit from the Augend and the resulted carry (COUT) bit which will be added to the next stage (b) 2's-Complement Form - Result obtained when a is added to the least significant bit position of a binary number in the 1's-complement form (c) Arithmetic/Logic Unit - Digital circuit used in computers to perform various arithmetic and logic operations (d) Sign Bit - Binary bit that is added to the leftmost position of a binary number to indicate whether that number represents a positive or a negative quantity (e) Overflow - When in the process of adding signed binary numbers a is generated from the MSB position of the number into the sign bit position (f) Accumulator - Principal register of an Arithmetic Logic Unit (ALU) (g) Parallel Adder - Digital circuit made from full adders and used to add all the bits from the addend and the Augend together and simultaneously _ 99 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition (h) Look-Ahead Carry - Ability of some parallel adders to predict, without having to wait for the carry to propagate through the full adders, whether or not a carry bit (C OUT) will be generated as a result of the addition, thus reducing the overall propagation delays (i) Negation (2's complementing)- It's the operation of converting a positive binary number to its negative equivalent or a negative binary number to its positive equivalent (j) B-Register - One of two flip-flop registers used by the ALU (Arithmetic-Logic Unit) 6.53 6.54 6.55 010010012 = 00000000010010012 = +7310 101011102 = 11111111101011102 = -8210 The general rule used to convert 8-bit to 16-bit signed binary numbers is as follows: If the signed bit of the 8-bit signed number is positive (0), then more 0s are added in front of the 8-bit number thereby, making it a 16-bit number with the same sign as the original 8-bit number If the signed bit of the 8-bit signed number is negative (1), then more 1s are added in front of the 8-bit number thereby, making it a 16-bit number with the same sign as the original 8-bit number _ 100 ... 4321 4321 F 165 0E9B - + 51BC } 0200 } 3FD1 } + } 41D1 16 locations= 168 4910 } } } 6. 17 (a) 77 16 = 11910 (b) 77 16 = +11910 (c) E5 16 = 22910 ; E5 16 = -2710 6. 18 One possibility... possibility is to convert each EX-OR to its NAND equivalents shown below: Then, convert ANDs and OR gate for COUT to their equivalent NAND representation 6. 19 6. 21 6. 22 After the PGT of the LOAD pulse,... 6. 45 (a) 6. 46 AHDL (b) (b) b[0] = (c) a[7] = (c) 0010110 z [6 0] = a[7 1] z[7] = a[0]; VHDL z (6 0)
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