WORLD'S #1 ACADEMIC OUTLINE ELE PART of FUNDAMENTALS OF ELECTRONIC DEVICES & BASIC ELECTRONIC CIRCUITS OPERATIONAL AMPLIFIERS DEFINITIONS - A basic ditlerential amplifier (see Electronics I Part One) enables mathematical ditlerence operation and can be modified to perform addition, integration and differentiation Hence, the differential amplitier is also designated as an Operational Amplifier (Op-Amp) Op-Amp represents, v ~ V Fig 111 essence, a hIgh-gam "" ­ electrol1lc cIrcuIt mtended A to amphfy the dlflerence 111 + Vo ~ vom the sIgnal voltages apphed v,,,, v to its two input terminals, namely, inverting (- ) and non-inverting (+) inputs (Fig 1) -In simple form (Fig 2), Fig an Op-Amp constitutes a Differential Pair output differential amplifier made Up of, for example, a pair of +~­ BJTs driven by a constant Non­ current source (I) JFETs inverting I and MOSFETs can also be IOput used as differential pairs -An -SLEW RATE: Maximum rate at which the output voltage can change (volts/microsecond) In ideal OP­ AMPs, slew-rate ~ 00 -OTHER PARAMETERS: (I) Bandwidth; (2) Maximum output current available when the output terminal is set to ground; (3) PSRR: Power supply rejection ratio: Change in input offset voltage to corresponding change in one of the power supply voltages (±V) Ideally, PSRR = 0; in practice, it is of the order of a few 11VIV OP-AMP OPERATIONAL PARAMETERS In reference to typical inverting (Fig 3, above right) andnon­ inverting (Fig 4) modes ofoperational characteristics: -INPUT BIAS CURRENT: This is the emitter current in the differential amplifier for active region operation of the pair of BJTs (e.g 0.0511A for 741 OP-AMP) which comes through R2 so that Vou' = (0.05 X 10-6 x R 2)volts This could be large enough to saturate the output Saturation is overcome by introducing R, = RdlR2 and made adjustable to compensate for input offset current due to any dissimilarities in the differ­ ential pair configuration (Fig 3) -INPUT OFFSET VOLTAGE (= ± 60mV): It is required at the input as a counter voltage to offset the tinite unbalance voltage due to unequal current flowing through the differential pair devices in the OP-AMP, so _ that this balancing gives zero output voltage -CMRR: When the OP-AMP is ideally balanced at the input, the output voltage = 0, i.e Vlnt = Vin2, and this circuit can reject common-mode signals due to its common-mode gain (Ae) = O For differential mode signals (Vln' - Vin2), the gain (Ad) ~~ The ratio Ad/Ae common-mode rejection ratio (CMRR) In practical OP-AMPs, Ae > and Ad < 00; or, CMRR is finite and indicates the extent of balance in the OP-AMP (A Igure of merit parameter) -OUTPUT VOLTAGE SWING: This is the peak output swing with reference to zero at the output It is limited by power supply voltages used (= 80 percent of power supply voltage ±V) -INPUT VOLTAGE SWING: Input common-mode voltage swing is limited by the saturation of the differ­ ential amplifier at the input: (= 30 percent of power supply voltage ±V) Fi~ ~ ,.~ ~:,- ~; j :.:- ~; j Source Circuit Sink Circuit LOGARITHMIC AMPLIFIER FREQUENCY ROLL-OFF It is the fall-off of the voltage gain at high frequencies This is indicated by gain-bandwidth product Roll-off to higher frequencies is achieved by frequency compensation (V ) V out k T =-I-In _'_n_ q alllR V OU! R~vcrsc INVERTING AMPLIFIER (VIRTUAL GROUND AMPLIFIER) a: Virtual Fig saturation current or E8 Juncti on : Tran sislOr a kl3 : l30hzmann Constant CHARGE AMPLIFIER R, Fig 10 Input (from a VOU( capac iti ve transducer); Vin Cr: Nominal capaci tan ce of the transducer charged by a voltage V input IDEAL OP-AMP CHARACTERISTICS - Nominal voltage gain, A ~ ~ -Input impedance (at both inputs), Zln ~ 00 -Output impedance, Zo ~ - Both transistors are idcntical ·Vo = -AVint = AVin2; or, if Vinl = Vin2, Vo = - Bandwidth (BW) ~ ~ - With bipolar transistors, it may be difficult to achieve a very high-input impedance -JFET and MOSFET provide high-input impedance capabilities ~ ~ LINEAR VOLTAGE-TO-CURRENT CONVERTERS R, ~ R J -Output impedance with feedback =' Output impedance of the OP-AMPxClosed-loop gain (Open-loop gain) - Node a is almost at ground potential -Closed-loop voltage gain Vout / Vin = -R2/RI -Input impedance = RI - Output impedance = Ro = v.In V out Fig 11 (1+~) R, PRECISION RECTIFIER & PEAK DETECTOR ~ VOO.'~ V"," '" ~v,"~ J, NON-INVERTING AMPLIFIER v Fig Precision Recti fier R2 Av=l + ­ Zln = R3 R Zout ~ Low Non-inverting input VOLTAGE FOLLOWER (UNITY GAIN AMPLIFIER) F,g ~ _ INTEGRATOR (LOW-PASS FILTER) c Fig - R 2: Provides negative feedback for low­ output impedance needs, but it also distorts the output dv o dt =-~ R.C V =_(_I_)Xf R.C V dt ,n Peak Detector Zill =A X Vi" ~ Z,,,,, (Rill (Device)( [Ro (Device)] A Unity Gain Amplifier The output voltage "follows" the input voltage Used as a buffer amplifier with high-input/low-output impedance reali zation REGULATED POWER SUPPLY DIFFERENTIATOR (HIGH-PASS FILTER) p ~ Fig Vin .-.t"·1~ RR.,' +A I- v "" f -Inverse operatIOn the integrator circuit The Zener diode offers a constant reference voltage (V z) Bias derived from the unregulated voltage (VII), via potential division by RI and Rl and the Zener reference voltage, are compared by an inverting amplifier to provide a stable output Voltage Vou' = V, (t + R./ R 2) and I, = (vou,- V,) / R3 Fig 13 LEVEL CLAMPING : g~>L".' 1fJffifb.:: A R, out + - The output is clamped to Zener voltage V, MOSFET DEFINITIONS • The device current is decided by one type of current carrier only (unipolar) • The device interior current is controlled by an electric field applicd in the path of the current carriers FET TYPES ·JFET (Junction Field Effect Transistor): In the JFET, the resistance of the current path is modulated by the application of bias voltages to PN junctions adjacent to it • MOSFET (Metal-Oxide Semiconductor FET): In MOSFET, there arc no junctions The controlling electric field is applied via an insulating layer to regulate the resistance of' a main conducting path • When V G is applied: This provides additional reverse-bias Therefore , pinch-off will occur at lower VI) and the corresponding VI)(s.') will also be smaller Hence, application of V G modulates the channel dimension and reduces In This is a depletion mode operation Channel current decreases as the gate voltage is increased DEFINITIONS ~ Induced channel devicel lnsulated Gate FET (IG FET) ·The gate is totally insulatcd rrom the semiconductor by a thin layer or Si0 • The voltage applied at the gate induces a conducting channel within the semiconductor and modulates its conductivity LINEAR OPERATION OF JFET Fig 15 ENHANCEMENT TYPE MOSFET Pinch-off locus Fig 16 FET OPERATION MODES Si02~ 100 to Slope: Go 300 A' (Thermally grown insulation layer) MOSFET OPERATION Fig 17 r - , GI Source Gate x-direction c- = Electron s ~ VI) Slope: Go No gate bias G ~ N+ [Yo: Contact potential, Na and Nd are acceptor and donor concentrations; €: Permittivity of the channel] Let V PO be the value of V G at which pinch-off occurs The corresponding change in In = O For V G < V po, where Go = channel conductance with zero bias (VG=O) condition: Go = (eNd~.) x IArea of cross-section of the channell Length of the channell e: electronic charge; ~c: electron mobility G +VJ) ~ -+1 + VG ++ +++ ~~.-, N+ Induced negat ive P-c pi charges Suppose no gate voltagc is applied Then, N+P junction at the source, as well as PN+ junction at the drain , are reverse-biased Thererore, no drain current flows Suppose a small +V G is applied at the gate T he positive voltage at the top of the Si0 dielectric would induce negativc charges below this layer These negative charges will deplete the holes of the P­ epilaycr, exposing ncgatively charged acceptor ions i.e a depletion layer will be tormed just below the gate as shown in Fig 17 A further increase in +V G will induce more and more negative charges below the gate, with the result being a copious accumulation of negative charges below the gate forming an induced­ layer of negative charges constituting a " channel" (induced channel) between the source and thc drain as shown in Fig 18 Fig 18 JFET OPERATION ~ \ -Nt Upon pinch-off: OUTPUT CHARACTERISTICS OF JFET I os =1 l] - 3VG+2(VG)~1 Vp 0" • ( g -_dlnsl -m dV -_ -I 0" C Vi) m I m vG ~ o 3VJ)l - 1- (VG)il - ­ VZ V =g P P -31 _ _ _ Il,_, - - G mil - Vp - = Conductance of the channel with zero bias g m == g mil ll - (VG Vp )}l "N+" /' N-tYPL'in(\ucccll:han1)c l \ •••• - Dep!ction laye r r',cpi N-type Induced Channel gm ~ Mutual/transfer conductance = Max g =g ::: ~ :=::::: Vp Transfer Characteristics: Suppose an additional bias V G is applied between the gates and the source terminals (Fig 14b): • Suppose, V G = O In the absence of drain current, the depletion layer is uniform along the channel As VI) increases, II) increases Corresponding voltage drop along the channel causes a wedge-shaped path due to reasons discussed before Upon pinch-ofl~ the drain current remains constant at a saturated value ) N+ P-('pi Suppose channel is lightly doped relative to the gates, i e Na(ga'e) » Nd(ch.nnel)' : Thickness of depletion [(Vo+VG)]} layer 111 the N-channells d n == 2E eN As V G changes, d n changes D +VJ) ~ I ~ Due to the appl ication of the voltage across source (S)-to-drain (D), electrons flow from S to (majority carrier flow) Thc path between S-to-O has an ohmic resistance Therefore, flow of electron current would cause a voltage drop and the potential at any point along this path (x-direction) increases from the source to drain (becoming more positive towards the drain end) Since the gates (tied together) are connected to the source, the N-region ofthe channel and the regions of the gate would form a reverse-biased PN junction The extent of reverse bias increases progressively from the source side to drain side Correspondingly, the depletion layers formcd will be wider near the drain side as shown Normally, the P-type gates (G I and G z) are heavily doped relativc to the N-channel region Therefore, channel has (relatively) high resistance Hence, the depletion laycr widens predominantly into the channel region Suppose Vo is increased Consequently, the depletion layer into the channel widens more As a result, eventually the two (top and bottom) depletion layers meet each other Therefore, the channel is closed , not permitting the flow of electrons through it This condition is known as pinch-off N+ drain Polysili P-typc cpitaxi a l substrate JFET: DEVICE OPERATION Fig 14a Si0 layer N+ source • Depletion mode operation: The controlling electric field reduces the number of carriers available for conduction • Enhancement mode operation: Application of electric field causes an increase in the majority-carrier density in the conducting regions of the transistor Once the channcl is induced between the Sand , the electrons flow through thi s channel, with the result bcing a drain current Therefi.)re, the induced channcl constitutes an ohmic path The conductivity of this channel is dependcnt on the magnitUde of Ve In other words, the channel conduc­ tivity is modulated by VG Thcreforc, the morc the VG , the more will be Il) Thus, the device operates in enhancement lllode COMMON-GATE AMPLIFIER MOSFET OUTPUT CHARACTERISTICS Fig 19 G ? VG Saturation region Pinch-otT locus 10 +++1+++ lOS IV d Common-gate (CG) FET amplifier circuit and its equivalent circuits Fig 25 • Vo (1l+ I )R L A v = '",gmRLfor vin rd +RL : Increasing ~ ~ = DifTuscd N-typc layer: Chanllel P-cpitaxial substrate Rj Vp VG - Fig 25 Common-Gate Amplifier S ~cCg) Ve- VT - Vo/2) I[)= ( V Vo=>ThlsIoversus VI) is valid as long as Vc; - Vex) > V T Note: L: Channel length At some gate voltage VC;I with Vex) = VI), the channel is turned open and the flow of charges along the channel becomes constant, i.e at Vo = VC;I - V T , ~cCg VC;-VT )2 =-' -"'O_L-_ ds I, r d » RL for rd» ~ _ _ "' _ '2 VT Analysis: Let voltage at x along the channel be Vex) I gmrd» RI +rd R L; il 11+1 gm Vo Ro = -:- = rd + (~+ I)Re '" rtl + ~RG Vos V =_1_11 = _u_1I)_I => C _V_o uVe v gm -~ g L2 c ~- D Depletion mode (; - When a positive bias is applied, more electrons are drawn into the channel causing more carrier population, i.e channel conductance is increased Hence, more current would now; or, an increase in +Ve would increase [0 => enhancement mode operation V-I character­ istics indicate that circuit operations of diffused-channel MOSFET are similar to thosc of JFET (~ S t+ : Amplitication factor) i······ I + o i G O -' t:::::::i=~ - Note: For CG configuration, the output resistance is very large and can be considered as infinite; the input resistance is relatively low Voltage gain is dependent on R L , and its maximum value is about~ CG configuration in FET is the counterpart orCB configuration in BJTs ~ Transconductance of the MOSFET I Il)s=Illv ~cCg( - v = - - VC;-VT =V 1> G T 20 )2 Vo =gm­ V-I CHARACTERISTICS OF ENHANCEMENT-TYPE MOSFET Fig 20 COMMON-SOURCE AMPLIFIER , VGs= V T Ohmic Region Normal symbolic representations of the JFETs and the MOSFETs are shown in Fig 22 Saturation Region VG \ Fig 22 N-channel JFET V DS NMOS output characteristics -Ohmic Region (Triode Region) Here VOS S; V GS - V T and the V -I characteristic is 10 = Kn'2(VGS - V'r)V IlS - V20s), where W = ~.Cox (W) and II = surface L L ox mobility of electrons: ~c = 800cm I volt-sec (in Silo Eo = permittivity of free space ( = 8.85 x 10 -14 F/cm) Eox = dielectric constant of Si0 ('" 4); tox = thickness of the oxide; Cox = EoEoxLW/tox Co,: Capacitance of SiOz layer Dividing locus between saturation and ohmic regions is given by substituting Vos = (Ves - V T): _ ' _ ~cCoxW 10 - Kn V os - - - - V os' 2L This locus is shown by the dotted line in Fig 20 -SATURATION REGION: Here, VI)S ;?: Ves - V T , and the current II) is approximately constant as shown in Fig 20 The transfer characteristic is obtained by replacing Vos by Ves - V T ; 10 = Kn (Ves - V T)2 A plot of the transfer characteristic is shown in Fig 20 -CUTOFF REGION: Here, Vc;s < V T, and thus 10 = O The device is OFF in this region and is used in switching applications in this mode K n = ~/'oEox 2t DIFFUSED-CHANNEL (DEPLETION-TYPE) MOSFET -Diffused-channel MOSFET can be operated both as depletion mode or as enhancement mode device -The device has a thin N-type layer of the same conductivity as source or drain and is diffused below the gate - When the gate has a small negative bias, the resulting positive charges in this diffused region cause the depletion layer (channel conductance) to be reduced Thus, negative bias on gate enables depletion mode operation P-channel JFET G~ G~ S NMOS PMOS FET FET J J D A common-source (CS) FET amplilier (with the dc biasing circuitry) and its small signal equivalent circuit are shown in Fig 26 , - _ , -+" VI) D Fig 26 + ,.- + o D Go19 Go19 s D S Fig 23 Approximate Low Frequency Equivalent Circuits 1, {,~l 1, s~s MOSFET JFET Fig 24 High Frequency Equivalent Circuit of a JFET G t ~' c" Cd:t+ g",v, COMMON-DRAIN AMPLIFIER f ds Current in an FET is carried by majority carriers drifting under the influence of an electric field, whereas in the bipolar transistor, current is transported by means of diffusing minority carriers Since drift velocities in semiconductors are usually very much higher than diffusion velocities, carrier transit times are much shorter in FETs than in bipolar transistors For this reason, one might expect FETs to have a much more extended high-frequency range than bipolar devices A limitation to the high-frequency performance or the switching speed of a FET is the gate-channel capacitance, which must be charged via the channel resistance The resulting time constant determines the upper limit of the frequency response The gain x bandwidth product, which can be derived from the equivalent circuit and equals gm/21tCg, is normally taken as afigure ofmerit to indicate the high-frequency response of a particular device V-V g -.!!! =Il ~; C g: Total gate capacitance Cg e L2 A common-drain (CD) FET amplifier (with the bi asing circuitry) and its small-signal equivalent circuit are shown in Fig 27 Ro= _VO Av= ~RL (I+~)RL +rd _ g mRL l+gmR L For gmRL » I, the voltage gain is close to unity The CD configuration is thererore called the source follower (SF), since the source voltage follows the input gate signal The CS conl1guration in FET is the counterpart of the CC configuration in 8.IT COMPARISON OF FET AMPLIFIERS N-CHANNEL JFET ~ Fig 28 Common-Source Amplifier Z ~ Yin ID Is V'I - K in;\;, V,,'" RD o ~ Parameters i ,t :!: V OD YV 'II IVy:, Vos + i1(V l R +~ S In gm A\, = Vin N-~~l~~~el MOSFET =" -t H> _-oV"lLt I" Symbol JO G o j 8 Symbol '1s G o j ~ V;n = V GS Vout = Vou -loRD = Vos G O- (a) o A = tl(Vou,l =-g R v - On-Slate: VGS> VT - Satration Region: Vus ~ VGS - VT io = K(vGS - VT)2(1 + AVoS) -Triode Region: Vns ~ VGS - VT iu = K[2(vGS - VT)vos - v2nsl - VA: A FET Parameter ~(Vin) - m (b) S I) (a) Conventional (b) When substratelbody " " connected to source Note: Different states and regions of operation: => Same as for N-channel JFET gmRL rd ~m - gmRL g mRI gm Ra + I *SF=Sourcc Follower Olher Parameters DepIction OP-AMPS REVISITED -INSTRUMENTATION AMPLIFIER - a high-perfor­ mance differential amplifier with high-input impedance - Vo = - (R4/ R3) (\ + R 2/R I) (VI - V 2) -Input impedance presented at both inputs tends to be infinity -Output impedance of the differential amplifier tends to be zero -Application: To amplify ditferential signal(s) from tran sducers / sensors - RI can be adjusted to achieve null-offset Fig 34 Common Source Amplifier , -_._ - i : Differential Amplifier i P-CHANNEL DEPLETION MOSFET P-CHANNEL JFET Fig 32 Common-Source Amplifier Fig 29 Common-Source Amplifier Vo + V, VDD + A RO Parameters ~? V;II = VGS - IsRs Vllut = -VU - II)RU = Vns - IsRs tl(V l _-_ R O_ A = O_"t_= , Common-Source Amplifier CD(SF)* CS XIII Rin Fig 31 [JI c=o W CG N-CHANNEL ENHANCEMENT MOSFET Parameters Parameters + V, ~pC,,~ W K - 2-L- Symbol JS '0 Vns j.1p: Hole mobility V;n = V GS Vou' = -VI)O - InRo Symbol (a) s (b) Common-Source Amplifier -v DU Symbol Symbol G ~' -oB ~ (a) = -g R tl(V;nl m G-l JS V;n = VGS Vout = VOl) - InRI) = VOS o ~B A = i1(Vout l "'-g R o v Z W ~(Vin) - m J'S (b) 10 ~O S (a) Conventional (b) When substratelbody "B" connected to source Note: Different states and regions of operation: => Same as for P-channel JFET (a) Conventional (b) When substrate/body " " connected to source Note: Different states and regions of operation: => Same as for N-channel JFET ~ (a) S ~ (b) ~ MOSFET JFET Go -J _ = tl(Voutl v OUI As for N-C hanncl Others A r=' -H ~_ ov 2L ­ As for P-Channel Other Parameters Dep iction RD Iln Co~ W K ~ or th is publication may be reproduced or tran s­ Customer Hotline #1.800.230.9522 ~ All rights reserved No part U 1l11lted in any form, or by an y mean s, electroni c or mechani cal, incl uding photocopy , recordmg, or any mlc)! mati on storage and retncval system, \\ llhout wntten pennl~ S I On from the pubh sher O ~ 154611 210 51310 ;;,~;~:, >-+ o VQ Parameters VT V, = VGS Vout = - Vno - loRo = VOS Fig 35 Fig 33 Parameters Yin -AC-COUPLED NON-INVERTING AMPLIFIE R: -Capacitivcly coupling an OP-AMP reduces the dc offset considerably - Provision of R3 is mandated to facilitate continuous dc path for each of the input terminals C, P-CHANNEL ENHANCEMENT MOSFET Fig 30 V OUl (a) Conventional (b) When substratelbody " 8" connected to source Note: Different states and regions of operation: => Same as for P-channel JFET N-CHANNEL DEPLETION MOSFET Common-Source Amplifier D Go I ~ = Vos A = tl(Voutl =-g R v i1(V;nl m I) -On-State: VGS ~ VT -Satration Region: VOS ~ VGS - VT io = K(VGS - VT)2(l + AVos) -Triode Region : Vos ~ VGS - VT iu = K/2(vGs- VT)VOS - V2os/ L=O Go -,l' We welcome your feedback so we can maintain and exceed your expectations P S Nool"""" C Eng , Fellow lEE fr~~~&'Z2kO~~~tfes at qUlcKsluay.com - A SUMMARY ON OP-AMPS -OP-AMPS in practical circuits o ffer performance matching theoretical estimations -An OP-AMP consists of: (a) An inverting input terminal; (b) A non-inverting input terminal; (e) An output terminal; (d) Two power supply terminals + and -, with a common circuit ground -Ideally, an OP-AMP responds to the two inputs (+v;nd and (-V;n2) to yield an output V" = A(v;n l - V;n2) ; A is known as open-loop gain, which is very large (Ideally A ~ ~; in practice, A - 104 to 10 ) - An ideal OP-AMP has an infinite input impedance (at both input terminals) and a zero output impedance - With a negative feedback, the closed-loop gains are : - For inverting input, V,,IV;III = R2/ RI - For non-inverting input, VJV;n2 = (I + R 2/R I) NOTE TO STUDENTS: Due 10 it s condensed formal use this QuickStudye gu ide il ~ an outline of the bas ics of Eledronics ~Uld not as a rep lacement for asslg!led course work 10200 1-2008 B ~trch arts [nc 12D8 ISBN-13: 978-157222530-5 ISBN-L0: 157222530-0 911~~l,lllll~III!~IJlj~IJIIIIMllrllilil