© DHBK 2005 Nội dung môn học Giới thiệu chung hệ vi xử lý Bộ vi xử lý Intel 8088/8086 Lập trình hợp ngữ cho 8086 Tổ chức vào liệu Ngắt xử lý ngắt Truy cập nhớ trực tiếp DMA Các vi xử lý thực tế 1/Chapter © DHBK 2005 Chương 6: Truy cập nhớ trực tiếp DMA • Giới thiệu DMA • Mạch DMAC 8237A Intel 2/Chapter © DHBK 2005 Giới thiệu DMA 3/Chapter © DHBK 2005 Mạch DMAC 8237A Intel 4/Chapter © DHBK 2005 Mạch DMAC 8237A Intel 5/Chapter • Although i8237A may not appear as a discrete component in recent PCs, it’s still there… (integrated in chipsets, ISPC) • The i8237A has four independent DMA channels • Original PC/XT design had one i8237A for four DMA channels • PC/AT used two i8237As to provide DMA channels • i8237A is programmable device and can be configured for single transfers, block transfers, Reads, Writes or Memory-toMemory transfers © DHBK 2005 Mạch DMAC 8237A Intel 6/Chapter • i8237A allows byte addressing for 8-bit data transfers • In the PC/AT design, a contrived 16-bit transfer design is implemented using the i8237A • i8237A uses a multiplexed address and data bus to reduce the device pin count  DB0 DB7 lines contain the data bus along with the high byte of the 16bit address bus  An external latch is required to demultiplex the address lines © DHBK 2005 Mạch DMAC 8237A Intel 7/Chapter © DHBK 2005 Mạch DMAC 8237A Intel 8/Chapter © DHBK 2005 Mạch DMAC 8237A Intel 9/Chapter © DHBK 2005 10 /Chapter6 How the PC uses the i8237A i8237A Address Latch and Page Registers I/O Mapped to MPU, read and write IOR IOW MEMR MEMW DMA Page Regrs HLDA EOP A8 A15 ADSTB i8237 DMA HRQ [A16 A19 for PC/XT] DMA Addr Latch DB0 DB7 four DMA channels A16 A23 A0 A7 A0 A7 DREQ0 DACK0 DREQ1 DACK1 DREQ2 DACK2 DREQ3 DACK3 Hi Q D CLR Floppy Controller 15 usecs OUT1 8253 (8254) Timer/ Counter © DHBK 2005 DMA Address Tracking 11 /Chapter6 • The i8237A has four registers for tracking memory addresses during a DMA block     BASE ADDRESS REGISTER BASE WORD COUNT REGISTER CURRENT ADDRESS REGISTER CURRENT WORD COUNT REGISTER © DHBK 2005 DMA in the PC/XT 12 /Chapter6 © DHBK 2005 13 /Chapter6 DMA Cascadation Cascaded i8237As in the PC/AT Cascaded i8237A DMA Controllers DREQ0 DACK0 i8237A Slave DREQ4 MPU HOLDA i8237A Master DREQ2 DACK2 DREQ3 DACK3 DACK4 HRQ DREQ1 DACK1 DREQ5 DACK5 DREQ6 DACK6 DREQ7 DACK7 © DHBK 2005 14 /Chapter6 PC/AT DMA Channel priorities • • • • DMA channel (DREQ0) has the highest priority DMA channel (DREQ7) has the lowest Note, when a DMA transfer is in session, it cannot be 'interrupted' by another DMA request, even if the DMA request is made by a higher priority DMA channel The current DMA transfer session will be completed before the pending DMA request is accepted © DHBK 2005 DMA Channels in the PC/AT   DMA Priority Pre-defined 8-bit or Use in PC/AT 16-bit DREQ0 Highest Memory Refresh* 8-bits DREQ1 Not defined 8-bits DREQ2 Floppy Disk 8-bits DREQ3 Not defined 8-bits DREQ4 Cascade not used DREQ5 Not defined 16-bits DREQ6 Not defined 16-bits Not defined 16-bits DREQ7 Lowest 15 /Chapter6