                         library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux1 is Port ( I : in STD_LOGIC; S0 : in STD_LOGIC; S1 : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (3 downto 0)); end demux1; architecture Behavioral of demux1 is begin process(I,S0,S1) begin if(S1='0' and S0='0')then Y