Inverse modeling for the study of 2D doping profile of submicron transistor using process and device simulation Chan Yin Hong National University of Singapore 2005 Inverse modeling for the study of 2D doping profile of submicron transistor using process and device simulation Submitted by CHAN YIN HONG (B.Eng.(Hons.), NUS) A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENY OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2005 ABSTRACT Direct quantitative determination of 2D doping profile of submicron MOSFETs continues to be elusive This project develops a technique to deduce 2D doping profile by the inverse modeling method combining process and device simulation Based on previous inverse modeling research, this project extends the inverse modeling technique by including process and device simulation together with multiple transistors electrical data used as target for matching Such methodology will allow a physical way of taking sensitive process steps such as implantation and high temperature annealing into account By combining electrical data like sub-threshold Id-Vg of multiple transistors for matching, the chance of getting a non-unique solution is kept to minimum An algorithm which spreads process simulation to multiple processors is developed to make the time consuming process simulation more efficient Since the final doping profile is based on simulation of doping activation and diffusion, instead of pure mathematical representation of doping profile as it was done in the past, the result can be predictive in nature A set of parameters obtained can be used for transistors produced with similar technology and process condition This allows fast characterization of multiple transistors without the repeated use of time consuming inverse modeling exercise and provides alternative to verify the uniqueness of solution obtained ACKNOWLEDGEMENTS First and foremost, I would like to express my sincere gratitude to Professor Chor Eng Fong and Professor Ganesh Samudra, my thesis supervisors, for their exceptional guidance, continuous encouragement and warm support Their insights in research work help me to overcome many hurdles in this project and without them, this project will not be possible I am also indebted to Dr Lap Chan and Dr Francis Benistant who spends much of valuable time in this project even after a day of hard work in CSM For personnel who held responsibility in the corporate world, it must be difficult and demanding to assign additional time and energy to supervise this academic activity Also, I would like to thanks CSM (Chartered Semiconductor Manufacturer) for the supportive material they provided me with Without their test wafer and extensive hardware/software support, many tests involved in this project would not be possible Finally I would like to complement Professor Dimitri A Antoniadis and Dr Ihsan J.Djomehri of MIT for their kind help and useful discussion when I was in United States CONTENTS Abstract Acknowledgement Contents 3-5 List of figures 6-8 List of tables List of symbols and abbreviations 10-11 Chapter one – Introduction 12 1.1 Motivation and aim 12-14 1.2 Previous work done using Inverse modeling technique 14-18 1.3 New inverse modeling approach to be examined in this project 18-22 1.4 Organization of the thesis 22-23 Chapter two – Theory 24 2.1 Physical models in process simulation 24-27 2.1.1 Implantation model selection and modification 27-33 2.1.2 Diffusion model selection 33-37 2.2 Physics behind device simulation 37-41 2.3 Selection of optimizing parameters 41-43 2.4 Selection of matching electrical data 43 2.5 Conclusion for chapter two 43-44 Chapter three – Computational techniques for simulation 45 3.1 Mathematical optimization algorithm 45-47 3.2 Flow of joint process/device simulation 47-48 3.3 Pre-inverse modeling calibration 49-50 -3- 3.4 Conclusion for chapter three 51 Chapter four – Inverse modeling results for combined process and device simulation using single transistor for optimization 52 4.1 Methodology explanation 52-53 4.2 Results of inverse modeling 54-61 4.3 Results on transistors with different process condition 61-65 4.4 Conclusion for chapter four 65 Chapter five – Inverse modeling results for combined process and device simulation using multiple transistors for optimization 66 5.1 Methodology explanation and rationale of approach 66-67 5.2 Results and discussion 67-73 5.3 Reliability of optimization and test for predictability 73-76 5.4 Conclusion for chapter five 77 Chapter six – Hybrid approach using only device simulation for fast optimization 78 6.1 Rationale, methodology and possible benefit 78-79 6.2 Discussion of results 80-82 6.3 Uniqueness of optimization result 82-86 6.4 Comparison of results from different inverse modeling method 6.5 Conclusion for chapter six 87-92 92 Chapter seven – Conclusion 93 7.1 Summary of project 93-94 7.2 Suggestion for future work 95 References 96-98 -4- Appendix A – Algorithm and source code for multiple processors utilization Appendix B – Algorithm and source code of TIF file modification -5- 99-103 104-110 LIST OF FIGURES Fig 1.1 Zoom in for net doping concentration along in transitional region under gate oxide using inverse modeling with pure device simulation 13 Fig 1.2 Illustration of Id-Vg sensitivity where depletion edge is moved by applying different Vds and Vbs bias 20 Fig 2.1 Process steps involved in TSUPREM4 simulation 25 Fig 2.2 Increased mesh density at critical area to give maximum accuracy 26 Fig 2.3 Demonstration of profile shape when using dual Pearson representation 29 Fig 3.1 Scheme for multi-processor utilization 48 Fig 3.2 CV matching plot for calibration of gate oxide thickness 49 Fig 4.1 Scheme for joint process/device inverse modeling exercise 53 Fig 4.2 0.11 micron nmos Id-Vg plot at Vb=0 55 Fig 4.3 0.11 micron nmos Id-Vg plot at Vb=-1 55 Fig 4.4 0.12 micron nmos Id-Vg plot at Vb=0 56 Fig 4.5 0.12 micron nmos Id-Vg plot at Vb=-1 56 Fig 4.6 0.13 micron nmos Id-Vg plot at Vb=0 57 Fig 4.7 0.13 micron nmos Id-Vg plot at Vb=-1 57 Fig 4.8 Lateral surface profile for 0.11 micron nmos and the initial guess 58 Fig 4.9 Lateral surface profile for 0.12 micron nmos and the initial guess 59 Fig 4.10 Lateral surface profile for 0.13 micron nmos and the initial guess 59 Fig 4.11 Comparsion of final lateral surface profile for nmos Lgate=110nm, 120nm and 130nm nmos 60 Fig 4.12 Comparsion of final lateral surface profile in transitional area for nmos Lgate=110nm, 120nm and 130nm nmos 60 Fig 4.13 Wafer one 0.13 micron nmos Id-Vg plot at Vb=0 61 -6- Fig 4.14 Wafer one 0.13 micron nmos Id-Vg plot at Vb=-1 63 Fig 4.15 Wafer two 0.13 micron nmos Id-Vg plot at Vb=0 63 Fig 4.16 Wafer two 0.13 micron nmos Id-Vg plot at Vb=-1 64 Fig 4.17 Wafer one lateral surface profile for 0.13 micron nmos 64 Fig 4.18 Wafer two lateral surface profile for 0.13 micron nmos 65 Fig 5.1 Algorithm for multi-transistors optimization 67 Fig 5.2 Sub-threshold Id-Vg match plot for multi-transistors inverse modeling 69 Fig 5.3 lateral surface profile for Lgate=110nm, 120nm and 130nm nmos using multiple-transistors optimization 71 Fig 5.4 lateral surface profile at transitional region for Lgate=110nm, 120nm and 130nm nmos using multiple-transistors optimization 71 Fig 5.5 Vertical net doping profile in silicon taken in the middle of the channel for 0.11, 0.12 and 0.13 micron nmos 72 Fig 5.6 2D active arsenic profile demonstrating ability to obtain individual dopant profile through new inverse modeling technique 73 Fig 5.7 Surface lateral profile comparing inverse modeling result and prediction from forward simulation 75 Fig 5.8 IdVg curves of 0.12 micron nmos at different substrate bias comparing experimental data and predicted data using parameters found by two transistors IM 76 Fig 6.1 Experimental and simulated Id-Vg plot for 0.11, 0.12, 0.13 micron nmos using hybrid inverse modeling method 81 Fig 6.2 Surface lateral profile result of 0.11, 0.12 and 0.13 micron nmos using hybrid inverse modeling 81 Fig 6.3 Surface lateral profile result in the transitional area of 0.11, 0.12 and 0.13 micron nmos using hybrid inverse modeling 82 Fig 6.4 Surface lateral profile result in the transitional area of 0.13 micron nmos using hybrid inverse modeling with different bias applied to the initial Gaussian mapping profile 83 Fig 6.5 Zoom in plot for figure 6.4 at around the metallurgical junction 84 -7- Fig 6.6 Surface lateral profile result in the transitional area of 0.13 micron nmos using hybrid inverse modeling with different bias applied to the initial tsuprem4 base profile 85 Fig 6.7 Zoom in plot for figure 6.6 at around the metallurgical junction 86 Fig 6.6 Comparison of lateral surface profile for 0.13nmos found by different inverse modeling methodology 87 Fig 6.7 Zoom in plot for figure 6.6 in the transitional area 88 Fig 6.8 2D net doping profile for 0.13 micron nmos obtained from single transistor IM method 89 Fig 6.9 2D net doping profile for 0.13 micron nmos obtained from multiple transistors IM method 90 Fig 6.10 2D net doping profile for 0.13 micron nmos obtained from hybrid IM method 90 -8- References Zachary K Lee, Michael B Mcllrath and Dimitri A Antoniadis., “TwoDimensional doping profile characterization of MOSFET’s by inverse modeling using I-V characteristics in the subthreshld region”, IEEE transactions on electron devices, vol.46, No.8, August 1999 Hirokazu Hayashi, Hideaki Matsuhashi, Koichi Fukuda and Kenji Nishi, “Inverse modeling and its application to MOSFET channel profile extraction”, IEICE TRANS Electron Vol E82-C, no.6 June 1999 Zachary K Lee, Michael B Mcllrath and Dimitri A Antoniadis., “Inverse modeling of MOSFET’s using I-V characteristics in the Subthreshold region”, IEEE transactions on electron devices 1997 G.Ouwerling, “Physical parameters extractions by inverse device modeling”, Solid-state electrons 3(6) p.757 1990 Ishan J.Djomehri, “Comprehensive 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md20000.wait med011 /arrange [fcx] while i=0 - 99 - if test ! -r final011 then echo "file one not ready" sleep 10 else echo "file one ready" sleep 10 exit fi done [arrange] // arrange data from medici for fitting #include #include #include main() { double idrain, vgatec, dummyv, vgate; char line1[150], line2[150], dummy[20], test[20], dummy1[20], dummy2[20]; int count1, count2, count3, fileno, count4; FILE *fin1; //define file names here static char *names[18]={ "aVd1.0E-02Vb0", "aVd0.21Vb0", "aVd0.31Vb0", "bVd1.0E-02Vb0", "bVd0.31Vb0", "bVd0.61Vb0", "cVd1.0E-02Vb0", "cVd0.31Vb0", "cVd0.61Vb0", "aVd1.0E-02Vb-1", "aVd0.21Vb-1", "aVd0.31Vb-1", "bVd1.0E-02Vb-1", "bVd0.31Vb-1", "bVd0.61Vb-1", "cVd1.0E-02Vb-1", "cVd0.31Vb-1", "cVd0.61Vb-1", - 100 - }; static char *enames[18]={ "AeVd1.0E-02Vb0", "AeVd0.21Vb0", "AeVd0.31Vb0", "BeVd1.0E-02Vb0", "BeVd0.31Vb0", "BeVd0.61Vb0", "CeVd1.0E-02Vb0", "CeVd0.31Vb0", "CeVd0.61Vb0", "AeVd1.0E-02Vb-1", "AeVd0.21Vb-1", "AeVd0.31Vb-1", "BeVd1.0E-02Vb-1", "BeVd0.31Vb-1", "BeVd0.61Vb-1", "CeVd1.0E-02Vb-1", "CeVd0.31Vb-1", "CeVd0.61Vb-1", }; //define number of files here fileno=18; // read in data for(count4=0; count4